Fast inhibit gate with applications

Claim 2

In combination, a plurality of sources of binary coded data; means utilizing the binary coded data from the sources; a two input AND gate connected between each source and the utilization means; and a priority resolver, each source having an output connected to the priority resolver for transmitting a request for access to the utilization means through the priority resolver, the priority resolver having an output for each AND gate associated with each source for enabling the AND gate to transmit the data from a source to the utilization means with the priority resolver including means for coupling the request for access signal from the highest priority source directly to the AND gate associated with that source, said priority resolver including electronic circuits having two input terminals and at least one output terminal, which circuit functions as an RS flip-flop for a first and a second combination of binary input signals and as a combinational logic element for a third combination of binary input signals, connected in the path of each request for access signal for all lower priority sources with the request for access signal being applied to one input terminal and the complement of the request for access signal being applied to the other input terminal, and means for additionally coupling the request for access signal from each higher priority source to the one input terminal of the electronic circuit to which the complement of the request for access signal of the associated source is connected.

Claim 3

In a computer system, in combination, a randomly accessible memory; a plurality of requestors such as data processors and multiplexors which may individually seek access to the memory; a controllable transmission gate between each requestor and the memory, each gate having a control terminal; a priority resolver, said resolver having individual inputs from each requestor and individual outputs associated with each requestor for separately controlling each transmission gate associated with a particular requestor; and a request for access control line from each requestor connected to the respective individual inputs of the priority resolver, the priority resolver comprising a first path for the access request signal from the highest priority request to the control terminal of the transmission gate associated with the highest priority requestor, and electronic circuits having two input terminals and an output terminal, which circuit functions as an RS flip-flop for a first and a second combination of binary input signals and as a combinational logic element for a third combination of binary input signals, one of said electronic circuits being connected between an associated lower priority requestor and the control terminal of its associated transmission gate said circuit in the path of the access request signal of each of said lower priority requestors, with one input terminal being connected directly to the request for access control line of each requester and the other input terminal of the associated requestor being connected to the access control line through an inverter, and circuit means for additionally coupling the request for access signal from each higher priority requestor to the said other input terminal Of each electronic circuit.

Claim 4

In a computer system, in combination, a randomly accessible memory; a plurality of requestors such as data processors and multiplexors which may individually seek access to the memory; a controllable transmission gate between each requestor and the memory, each gate having a control terminal; a priority resolver, said resolver having individual inputs from each requestor and individual outputs associated with each requestor for separately controlling each transmission gate associated with a particular requestor; and a request for access control line from each requestor connected to the respective individual inputs of the priority resolver, the priority resolver comprising a first path for the access request signal from the highest priority request to the control terminal of the transmission gate associated with the highest priority requestor, and electronic circuits having two input terminals and an output terminal, which circuit functions as an RS flip-flop for a first and a second combination of binary input signals and as a combinational logic element for a third combination of binary input signals, one of said electronic circuits being connected between an associated lower priority requestor and the control terminal of its associated transmission gate said circuit in the path of the access request signal of each of said lower priority requestors, with one input terminal being connected directly to the request for access control line of each requester and the other input terminal of the associated requestor being connected to the access control line through an inverter, and circuit means for additionally coupling the request for access signal from each higher priority requestor to the said other input terminal Of each electronic circuit.

Claim 5

Method of granting priority of access to a randomly accessible memory to one requestor over another in a computer system having a plurality of memory modules; a plurality of requestors capable of communicating with one or more of the memory modules; and a memory control unit for one or more memory modules, with the memory control unit including address cross-routing circuitry in the path between the requestors and a particular memory module, comprising the steps of identifying the memory module requested in response to an access request by a requestor, determining whether the requested memory module is idle, generating a request recognized signal for each requestor seeking access to a memory module, resolving the priority of competing requestors to an identified module in the address cross-routing circuitry by applying each request recognized signal to a priority resolution circuit in the address cross-routing circuitry, and a response to the output of the priority resolution circuit enabling access to the identified memory from the highest priority requestor seeking access thereto provided the identified memory module is idle.

Claim 6

Method of granting priority of access to a randomly accessible memory to one requestor over another in a computer system having a plurality of memory modules; a plurality of requestors capable of communicating with one or more of the memory modules; and a memory control unit for one or more memory modules, with the memory control unit including address cross-routing circuitry in the path between the requestors and a particular memory module, comprising the steps of identifying the memory module requested in response to an access request by a requestor, determining whether the requested memory module is idle, generating a request recognized signal for each requestor seeking access to a memory module, resolving the priority of competing requestors to an identified module in the address cross-routing circuitry by applying each request recognized signal to a priority resolution circuit in the address cross-routing circuitry, and a response to the output of the priority resolution circuit enabling access to the identified memory from the highest priority requestor seeking access thereto provided the identified memory module is idle.

Claim 7

In a computer system having a plurality of requestor units made up of processors and/or multiplexors, a plurality of randomly accessible memories and a plurality of memory control units connected to control access to each memory in a specific group of memories; means in said memory control units for selectively coupling a requestor unit to a selected memory, said coupling means including control, circuit means for cross-routing the address data from said requestor unit to a selected memory; and circuit means for controlling the cross-routing means a cross-routing control circuit including a means for granting access to a particular memory module to a highest priority requestor and for generating an access granted signal for the said requestor granted access, the address cross-routing means including controllable gates for transmitting each bit of memory address data for each requestor unit, means for connecting the output of the controllable gates for the comparable individual bits of address data from each requestor, and a circuit means for enabling the controllable gates of the highest priority requestor to which access has been granted in response to the application of access granted signals from the cross-routing control circuit.

Claim 8

In a computer system having a plurality of requestor units made up of processors and/or multiplexors, a plurality of randomly accessible memories and a plurality of memory control units connected to control access to each memory in a specific group of memories; means in said memory control units for selectively coupling a requestor unit to a selected memory, said coupling means including control, circuit means for cross-routing the address data from said requestor unit to a selected memory; and circuit means for controlling the cross-routing means a cross-routing control circuit including a means for granting access to a particular memory module to a highest priority requestor and for generating an access granted signal for the said requestor granted access, the address cross-routing means including controllable gates for transmitting each bit of memory address data for each requestor unit, means for connecting the output of the controllable gates for the comparable individual bits of address data from each requestor, and a circuit means for enabling the controllable gates of the highest priority requestor to which access has been granted in response to the application of access granted signals from the cross-routing control circuit.

Claim 9

A data transmission system having in combination: a plurality of sources of binary coded data; means for utilizing the binary coded data from the sources; a transmission gate with an enabling input terminal, at least one other input terminal and one output terminal, each gate being connected to an associated source at one of said other terminals and to the utilization means at said output terminal; and a priority resolver, each source having an output connected to the priority resolver for transmitting to the priority resolver a signal for requesting access to the utilization means, the priority resolver comprising means for coupling the request for access signal from the highest priority source directly to the enabling terminal of the transmission gate associated with that source, said priority resolver further comprising electronic circuits having two input terminals and at least one output terminal, which circuits function as an RS flip-flop for a first and a second combination of binary input signals and as a combinational logic element for a third combination of binary input signals, one of said electronic circuit being connected in the path of each request for access signal for all lower priority sources to the enabling terminal of the associated transmission gate with the request for access signal being applied to one input terminal of the electronic circuit and the complement of the request for access signal being applied to the other input terminal, and means for additionally coupling the request for access signal from each higher priority source to the one input terminal of the electronic circuit to which the complement of the request for access signal of the associated source is connected, the priority resolver having an output coupled to the enabling terminal of each transmission gate associated with each source for enabling the transmission gate to transmit the data from a source to the utilization means.

Claim 10

A data transmission system having in combination: a plurality of sources of binary coded data; means for utilizing the binary coded data from the sources; a transmission gate with an enabling input terminal, at least one other input terminal and one output terminal, each gate being connected to an associated source at one of said other terminals and to the utilization means at said output terminal; and a priority resolver, each source having an output connected to the priority resolver for transmitting to the priority resolver a signal for requesting access to the utilization means, the priority resolver comprising means for coupling the request for access signal from the highest priority source directly to the enabling terminal of the transmission gate associated with that source, said priority resolver further comprising electronic circuits having two input terminals and at least one output terminal, which circuits function as an RS flip-flop for a first and a second combination of binary input signals and as a combinational logic element for a third combination of binary input signals, one of said electronic circuit being connected in the path of each request for access signal for all lower priority sources to the enabling terminal of the associated transmission gate with the request for access signal being applied to one input terminal of the electronic circuit and the complement of the request for access signal being applied to the other input terminal, and means for additionally coupling the request for access signal from each higher priority source to the one input terminal of the electronic circuit to which the complement of the request for access signal of the associated source is connected, the priority resolver having an output coupled to the enabling terminal of each transmission gate associated with each source for enabling the transmission gate to transmit the data from a source to the utilization means.

Claim 11

The combination in accordance with claim 5 wherein the first and second combination of binary input signals are a binary 1,0 and a binary 0,1, and the third combination of binary input signals is a binary 1,1.

Claim 12

The combination in accordance with claim 5 wherein the electronic circuit comprises: a first OR gate having one input terminal connected as one input terminal of the electronic circuit and a second input terminal, a first inverter connected to the output of the first OR gate, a second OR gate having one input terminal connected as the other input terminal of the electronic circuit and a second input terminal, a second inverter connected to the output of the second OR gate, means for coupling the output of the first inverter to the second input terminal of the second OR gate, means for coupling the output of the second inverter to the second input terminal of the first OR gate, and means for coupling the output of one of the inverters to the output terminal.