US3753014A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fast inhibit gate with applications
Assignee: Unisys Corp
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Filing: 1971-03-15
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Granted: 1973-08-14
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Expires: 1991-03-15
Abstract
Abstract An electronic circuit that has two input terminals and is responsive to three combinations of binary input signals is useful as a fast inhibit gate. The electronic circuit functions as an RS flip-flop for two of the combinations of binary input signals and as a combinational logic element for the third combination, which is the combination of a binary 1 on each input. Binary data to be transferred through the circuit is applied to one input terminal with the complement being applied to the other input terminal. An inhibit signal in the form of a binary 1 is applied to the same terminal to which the complement of the data is connected. In this way the inhibit signal may be applied directly to the electronic circuit rather than through additional logic elements with their attendant delay.
Inventors
- 👤 R Kronies
- 👤 J Coupland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 23:33
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/18; H03K19/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
89 words
Method of employing as a fast inhibit gate an electronic circuit designed to function as an RS flip-flop having a set input terminal, a reset input terminal, and a single output terminal comprising the steps of applying a binary 1 to be transferred through the circuit to the set terminal, applying the complement of the binary 1 to the reset terminal, and selectively applying a binary 1 to the reset terminal to inhibit the transfer to the output of the circuit of the binary 1 on the set terminal.
Claim 2
Dependent Claim
89 words
Method of employing as a fast inhibit gate an electronic circuit designed to function as an RS flip-flop having a set input terminal, a reset input terminal, and a single output terminal comprising the steps of applying a binary 1 to be transferred through the circuit to the set terminal, applying the complement of the binary 1 to the reset terminal, and selectively applying a binary 1 to the reset terminal to inhibit the transfer to the output of the circuit of the binary 1 on the set terminal.
Claim 3
Dependent Claim
128 words
A fast inhibit gate between a source of binary coded data and a utilization means comprising an electronic circuit having two input terminals and at least one output terminal, which circuit functions as an RS flip-flop for a first and a second combination of binary input signals and as a combinational logic element for a third combination of binary input signals; means for connecting the output of the source to one of the input terminals; means for connecting the binary complemenT of the output of the source to the other input terminal; and means for connecting a source of binary inhibit signal in the form of a binary 1 to the input terminal of the circuit that would be the reset terminal when operating as an RS flip-flop.
Claim 4
Dependent Claim
128 words
A fast inhibit gate between a source of binary coded data and a utilization means comprising an electronic circuit having two input terminals and at least one output terminal, which circuit functions as an RS flip-flop for a first and a second combination of binary input signals and as a combinational logic element for a third combination of binary input signals; means for connecting the output of the source to one of the input terminals; means for connecting the binary complemenT of the output of the source to the other input terminal; and means for connecting a source of binary inhibit signal in the form of a binary 1 to the input terminal of the circuit that would be the reset terminal when operating as an RS flip-flop.
Claim 5
Dependent Claim
130 words
A fast inhibit gate circuit comprising an electronic device having a first and a second input terminal and at least one output terminal and functioning as an RS flip-flop for a binary 1,0 input on the two input terminals and for a binary 0,1 input on the two input terminals and as a combinational logic element for a binary 1,1 on the two input terminals; means for connecting a source of binary coded data to the first input terminal; means for connecting a source of a binary inhibit signal in the form of a binary 1 to the second input terminal; and an inverter circuit connected between the two input terminals for applying to the second input terminal the complement of the binary input applied to the first input terminal.
Claim 6
Dependent Claim
130 words
A fast inhibit gate circuit comprising an electronic device having a first and a second input terminal and at least one output terminal and functioning as an RS flip-flop for a binary 1,0 input on the two input terminals and for a binary 0,1 input on the two input terminals and as a combinational logic element for a binary 1,1 on the two input terminals; means for connecting a source of binary coded data to the first input terminal; means for connecting a source of a binary inhibit signal in the form of a binary 1 to the second input terminal; and an inverter circuit connected between the two input terminals for applying to the second input terminal the complement of the binary input applied to the first input terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-13 | 1977-02-12 | 1977-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-13 | 1981-02-12 | 1981-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-13 | 1985-02-12 | 1985-08-14 | $7700.00 | Window Closed / Lapsed |