US3909802A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Diagnostic maintenance and test apparatus
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1974-04-08
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Granted: 1975-09-30
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Expires: 1994-04-08
Abstract
Abstract Diagnostic apparatus couples to a control store of a microprogrammed peripheral processor and is used to cycle the store in a plurality of different modes. The diagnostic apparatus includes mode control circuits which when set to a first mode, cause an instruction bit pattern established by a plurality of switches to be loaded into the local register of the control store when the apparatus detects that a predetermined address established by a set of address switches of the apparatus compares to the address stored in the address register of the control store. During the following cycle, the switch established instruction bit pattern substituted for the instruction stored at the location designated by the address switches is executed. When the diagnostic apparatus is set to operate in a second mode, the switches are set to establish a branch type instruction containing an address corresponding to a starting address in the store to be repeated of a microprogram routine. Each time the diagnostic apparatus detects a comparison, it forces the store and processor to a known state. During a following cycle, the microinstruction is loaded into the local register and executed causing the store to branch to the routine specified for execution.
Inventors
- 👤 Jr Frank V Cassarino
- 👤 Edwin J Pinheiro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:13
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/268; G06F11/00; G06F11/22; G06F11/26; G06F11/273
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
292 words
A diagnostic system for a microprogrammed processing unit including an unalterable addressable control store having a plurality of storage locations for storing microinstruction words, an address register means coupled to said control store for referencing said storage locations, output register means coupled to said control store for storing temporarily microinstruction words read out from referenced locations during cycles of operation and decoder means coupled to said output register for decoding said microinstruction word contents to generate signals to control the operations of said processing unit, said diagnostic system comprising: a first plurality of switching means for generating address signals designating a storage location of said control store whose contents are to be substituted; comparator means coupled to receive said address signals from said first plurality of switches and being coupled to receive signals from said address register means, said comparator means being operative upon detecting a true comparison between said address signals to generate an output signal; a second plurality of switching means for generating a substitute microinstruction bit pattern, said second plurality of switching means being coupled to said output register means; and, control means coupled to said comparator means and to said control store, said control means including logic means coupled to said output register and to said control store, said logic means being operative in response to said output signal to generate first and second signals respectively for loading signals representative of said substitute microinstruction bit pattern into said output register means and for inhibiting said control store from reading out the microinstruction word contents of the storage location addressed during that cycle of operation thereby enabling generation of said signals for said controlling of said processing unit in accordance with the coding of said substitute microinstruction bit pattern.
Claim 2
Dependent Claim
292 words
A diagnostic system for a microprogrammed processing unit including an unalterable addressable control store having a plurality of storage locations for storing microinstruction words, an address register means coupled to said control store for referencing said storage locations, output register means coupled to said control store for storing temporarily microinstruction words read out from referenced locations during cycles of operation and decoder means coupled to said output register for decoding said microinstruction word contents to generate signals to control the operations of said processing unit, said diagnostic system comprising: a first plurality of switching means for generating address signals designating a storage location of said control store whose contents are to be substituted; comparator means coupled to receive said address signals from said first plurality of switches and being coupled to receive signals from said address register means, said comparator means being operative upon detecting a true comparison between said address signals to generate an output signal; a second plurality of switching means for generating a substitute microinstruction bit pattern, said second plurality of switching means being coupled to said output register means; and, control means coupled to said comparator means and to said control store, said control means including logic means coupled to said output register and to said control store, said logic means being operative in response to said output signal to generate first and second signals respectively for loading signals representative of said substitute microinstruction bit pattern into said output register means and for inhibiting said control store from reading out the microinstruction word contents of the storage location addressed during that cycle of operation thereby enabling generation of said signals for said controlling of said processing unit in accordance with the coding of said substitute microinstruction bit pattern.
Claim 3
Dependent Claim
78 words
The system of claim 1 wherein said control means includes mode control means for establishing a plurality of modes for cycling said control store, said mode control means being coupled to said logic means and operative when in a first mode to condition said logic means for generating said first and second signals upon each occurrence of said output signal for enabling said controlling of said processing unit in accordance with the coding of said microinstruction bit pattern.
Claim 4
Dependent Claim
82 words
The system of claim 2 wherein said mode control means includes: a plurality of bistable storage means, eacn individually coupled to said logic means, input switch selection means coupled individually to each of said bistable storage means, said input switch selection means being operative to switch a predetermined one of said bistable storage means from a first state to a second state in accordance with the positioning of said switch selection Means for establishing said first mode of said plurality of modes.
Claim 5
Dependent Claim
40 words
The system of claim 2 wherein said first and second plurality of switching means each includes a plurality of manually controlled switch circuit means for generating binary coded signals corresponding to said address signals and said substitute microinstruction bit pattern.
Claim 6
Dependent Claim
38 words
The system of claim 1 wherein said second plurality of switching means are set to generate a predetermined microinstruction bit pattern defining a no operation type microinstruction for bypassing the microinstruction word stored at said storage location designated.
Claim 7
Dependent Claim
216 words
The system of claim 1 wherein said second plurality of switching means are conditioned to generate a predetermined type of microinstruction bit pattern for causing said store to return to a predetermined storage location within said store and wherein said control means includes; mode control means coupled to said logic means; reset switching means coupled to said logic means; and reset control means coupled to said reset switching means, said comparison means, said address register means and to storage devices within said processing unit, said mode control means and said reset switching means when set to a first mode conditioning said reset control means to generate in response to said output signal a reset control signal for clearing said address register means to a predetermined address and said storage devices to a known state and said reset control means being coupled to said logic means and operative at the termination of said reset control signal to condition said logic means for generating said first and second control signals for said enabling of said controlling of said processing unit in accordance with the coding of said substitute microinstruction bit pattern causing said processing unit to proceed through the execution of a given microinstruction sequence in the same manner independent of the results of executing said sequence previously.
Claim 8
Dependent Claim
54 words
The system of claim 6 wherein said reset switching means when set to a second mode inhibiting operation of said reset control means and said logic means being operative to cause said store to cycle between storage locations defined by said first plurality of switching means and said predetermined type of microinstruction bit pattern.
Claim 9
Dependent Claim
44 words
The system of claim 6 wherein said predetermined type of microinstruction bit pattern includes an op code field coded to specify an unconditional branch operation and a branch address field coded to designate said predetermined storage location defining a microinstruction loop including said sequence.
Claim 10
Dependent Claim
114 words
The system of claim 6 wherein said mode control means includes: a plurality of bistable storage means, each individually coupled to said logic means, input switch selection means coupled individually to each of said bistable storage means, said input switch selection means being operative to switch a predetermined one of said bistable storage means from a first state to a second state in accordance with the positioning of said switch selection means for establishing said firse mode of said plurality of modes and wherein said reset switching means includes a manually controlled switch circuit means having first and second positions, said switch circuit operating in said first mode when placed in said first position.
Claim 11
Dependent Claim
49 words
The system of claim 6 wherein said reset control means including counter means operative to generate said reset control signal so as to have a predetermined time duration for enabling said clearing of all of said processing unit storage devices required to place said unit in said known state.
Claim 12
Dependent Claim
33 words
The system of claim 6 wherein said first plurality of switching means are set to designate a storage location having an address one less than the storage location storing the microinstruction being substituted.
Claim 13
Dependent Claim
93 words
The system of claim 8 wherein said diagnostic system further includes branch control means coupled to said adDress register means and to receive said microinstruction word contents, said branch control means being responsive to predetermined type microinstruction words to perform testing of signals representative of the occurrence of different external and internal events indicated by the states of said storage devices, said branch control means being conditioned upon said clearing of said address register means and said storage devices to sequence said control store through said loop each time in the same manner.
Claim 14
Dependent Claim
101 words
The system of claim 6 wherein said diagnostic system further includes: a third plurality of switching means for generating address for designating a storage location used to synchronize the cycling of said control store to an auxiliary device; comparator means coupled to said address register means and to said third plurality of switching means, said comparator means being operative to generate a control signal upon detecting a true comparison between said signals; and, output generating means coupled to said comparator means and operative to generate an output synchronizing pulse for said device in response to each occurrence of said control signal.
Claim 15
Dependent Claim
78 words
The system of claim 13 wherein said address register means includes: an address register coupled to said store; a plurality of return address registers individually coupled to said address register; an increment register individually coupled to said plurality of said return registers and to said address register and said reset control means generating a plurality of signals for conditioning each of said registers to be cleared to said known state forcing said address register to said initial address.
Claim 16
Dependent Claim
17 words
The system of claim 14 wherein said initial address is coded as an all zero address code.
Claim 17
Dependent Claim
257 words
A diagnostic maintenance apparatus for controlling the operation of a microprogrammed processing unit including an unalterable addressable control store having a plurality of storage locations for storing sequences of microinstructions, address storage means coupled to said control store for referencing said storage locations, output register means coupled to said control store for storing temporarily the microinstruction contents read out from storage locations referenced during cycles of operation and decoder means coupled to said output register means for decoding said microinstruction contents for generating control signals therefrom, said diagnostic maintenance apparatus comprising: a first plurality of switching means for generating a first set of coded signals designating a storage location within said control store whose contents are to be substituted with another microinstruction; comparator means coupled to receive said first set of coded signals and coupled to receive signals from said address storage means, said comparator means being operative to generate an output signal signaling a true comparison between said signals; a second plurality of switching means coupled to said output register means for generating a second set of coded signals corresponding to said another microinstruction; and, control means coupled to said comparator means and to said output register means, said control means including signal generating means operative in response to said output signal to generate signals for conditioning said control store and said output register means for enabling the substitution of said another microinstruction in place of the microinstruction contents of the microinstruction designated by said first set of coded signals for decoding by said decoder means.
Claim 18
Dependent Claim
257 words
A diagnostic maintenance apparatus for controlling the operation of a microprogrammed processing unit including an unalterable addressable control store having a plurality of storage locations for storing sequences of microinstructions, address storage means coupled to said control store for referencing said storage locations, output register means coupled to said control store for storing temporarily the microinstruction contents read out from storage locations referenced during cycles of operation and decoder means coupled to said output register means for decoding said microinstruction contents for generating control signals therefrom, said diagnostic maintenance apparatus comprising: a first plurality of switching means for generating a first set of coded signals designating a storage location within said control store whose contents are to be substituted with another microinstruction; comparator means coupled to receive said first set of coded signals and coupled to receive signals from said address storage means, said comparator means being operative to generate an output signal signaling a true comparison between said signals; a second plurality of switching means coupled to said output register means for generating a second set of coded signals corresponding to said another microinstruction; and, control means coupled to said comparator means and to said output register means, said control means including signal generating means operative in response to said output signal to generate signals for conditioning said control store and said output register means for enabling the substitution of said another microinstruction in place of the microinstruction contents of the microinstruction designated by said first set of coded signals for decoding by said decoder means.
Claim 19
Dependent Claim
74 words
The system of claim 16 wherein said control means includes mode control means for establishing a plurality of modes for cycling said control store, said mode control means being coupled to said signal generating means and operative when in a first mode to condition said generating means for generating said signals upon each occurrence of said output signal for enabling saId controlling of said processing unit in accordance with the coding of said microinstruction.
Claim 20
Dependent Claim
82 words
The system of claim 17 wherein said mode control means includes: a plurality of bistable storage means, each individually coupled to said generating means, input switch selection means coupled individually to each of said bistable storage means, said input switch selection means being operative to switch a predetermined one of said bistable storage means from a first state to a second state in accordance with the positioning of said switch selection means for establishing said first mode of said plurality of modes.
Claim 21
Dependent Claim
38 words
The system of claim 17 wherein said first and second plurality of switching means each includes a plurality of manually controlled switch circuit means for generating binary coded signals corresponding to said first and second sets of signals.
Claim 22
Dependent Claim
35 words
The system of claim 16 wherein said second plurality of switching means are set to generate a predetermined microinstruction defining a no operation type microinstruction for bypassing the microinstruction stored at said storage location designated.
Claim 23
Dependent Claim
205 words
The system of claim 16 wherein said second plurality of switching means are conditioned to generate a predetermined type of microinstruction for causing said store to return to a predetermined storage location within said store and wherein said control means includes; mode control means coupled to said generating means; reset switching means coupled to said generating means; and reset control means coupled to said reset switching means, said comparator means, said address storage means and to storage devices within said processing unit, said mode control means and said reset switching means when set to a first mode conditioning said reset control means to generate in response to said output signal a reset control signal for clearing said address storage means and said storage devices to a known state and said reset control means being coupled to said generating means and operative at the termination of said reset control signal to condition said generating means for generating said signals for said enabling of said controlling of said processing unit in accordance with the coding of said substitute microinstruction as to have said processing unit proceed through the execution of a given microinstruction sequence in the same manner independent of the results of executing said sequence previously.
Claim 24
Dependent Claim
54 words
The system of claim 21 wherein said reset switching means when set to a second mode inhibiting the operation of said reset control means and said generating means being operative to cause said store to cycle only return storage locations defined by said first plurality of switching means and said predetermined type of microinstruction.
Claim 25
Dependent Claim
43 words
The system of claim 21 wherein said predetermined type of microinstruction includes an op code field coded to specify an unconditional branch operation and a branch address field coded to designate the said predetermined storage location defining a microinstruction loop including said sequence.
Claim 26
Dependent Claim
114 words
The system of claim 21 wherein said mode control means includes: a plurality of bistable storage means, each individually coupled to said generating means, input switch selection means coupled individually to each of said bistable storage means, said input switch selection means being operative to switch a predetermined one of said bistable storage means from a first state to a second state in accordance with the positioning of said switch selection means for establishing said first mode of said plurality of modes and wherein said reset switching means includes a manually controlled switch circuit means having first and second positions, said switch circuit operating in said first mode when placed in said first position.
Claim 27
Dependent Claim
49 words
The system of claim 21 wherein said reset control means including counter means operative to generate said reset control signal so as to have a predetermined time dUration for enabling said clearing of all of said processing unit storage devices required to place said unit in said known state.
Claim 28
Dependent Claim
33 words
The system of claim 20 wherein said first plurality of switching means are set to designate a storage location having an address one less than the storage location storing the microinstruction being substituted.
Claim 29
Dependent Claim
93 words
The system of claim 23 wherein said diagnostic system further includes branch control means coupled to said address storage means and to receive said microinstruction word contents, said branch control means being responsive to predetermined type of microinstructions to perform testing of signals representative of the occurrence of different external and internal events indicated by the states of said storage devices, said branch control means being conditioned upon said clearing of said address storage means and said storage devices to sequence said control store through said loop each time in the same manner.
Claim 30
Dependent Claim
101 words
The system of claim 21 wherein said diagnostic system further includes: a third plurality of switching means for generating address for designating a storage location used to synchronize the cycling of said control store to an auxiliary device; comparator means coupled to said address register means and to said third plurality of switching means, said comparator means being operative to generate a control signal upon detecting a true comparison between said signals; and, output generating means coupled to said comparator means and operative to generate an output synchronizing pulse for said device in response to each occurrence of said control signal.
Claim 31
Dependent Claim
271 words
For a microprogrammed peripheral controller including processing means for processing commands involving data transfer operations, a plurality of storage registers for storing status and information required for said processing, a microprogrammed control unit including a read only store for storing a plurality of microinstructions, an address register for referencing said microinstructions, an output register coupled to said store for storing temporarily referenced microinstructions during the cycling of said store for decoding into signals to direct said processing of said commands and branch control means coupled to said store, said address register and to different points within said controller for sequencing said read only store in response to testing for the presence of certain conditions within said controller, maintenance control apparatus comprising: a first plurality of switching means for generating a set of address signals designating a storage location of said read only store whose contents are to be substituted; comparison means coupled to receive said address signals and being coupled to receive signals from said address register, said comparison means being operative upon detecting an identical comparison between said signals to generate an output signal; a second plurality of switching means for generating coded microinstruction bit pattern signals, said second plurality of switching means being coupled to said output register; and, control means coupled to said comparison means, said control means including gating means coupled to said output register, said gating means being operative in response to said output signal to condition said output register for receiving in substitution for the microinstruction being read out of said designating storage location said coded microinstruction bit pattern signals for said decoding into signals.
Claim 32
Dependent Claim
271 words
For a microprogrammed peripheral controller including processing means for processing commands involving data transfer operations, a plurality of storage registers for storing status and information required for said processing, a microprogrammed control unit including a read only store for storing a plurality of microinstructions, an address register for referencing said microinstructions, an output register coupled to said store for storing temporarily referenced microinstructions during the cycling of said store for decoding into signals to direct said processing of said commands and branch control means coupled to said store, said address register and to different points within said controller for sequencing said read only store in response to testing for the presence of certain conditions within said controller, maintenance control apparatus comprising: a first plurality of switching means for generating a set of address signals designating a storage location of said read only store whose contents are to be substituted; comparison means coupled to receive said address signals and being coupled to receive signals from said address register, said comparison means being operative upon detecting an identical comparison between said signals to generate an output signal; a second plurality of switching means for generating coded microinstruction bit pattern signals, said second plurality of switching means being coupled to said output register; and, control means coupled to said comparison means, said control means including gating means coupled to said output register, said gating means being operative in response to said output signal to condition said output register for receiving in substitution for the microinstruction being read out of said designating storage location said coded microinstruction bit pattern signals for said decoding into signals.
Claim 33
Dependent Claim
68 words
The controller of claim 29 wherein said control means includes mode control means for establishing a plurality of modes for cycling said read only store, said mode control means being coupled to said gating means and operative when in a first mode to condition said gating means upon each occurrence of said output signal for enabling said output register for receiving said microinstruction bit pattern signals for decoding.
Claim 34
Dependent Claim
38 words
The controller of claim 29 wherein said second plurality of switching means are set to generate predetermined microinstruction bit pattern signals defining a no operation type microinstruction for bypassing the microinstruction word stored at said storage location designated.
Claim 35
Dependent Claim
201 words
The controller of claim 29 wherein said second plurality of switching means are conditioned to generate a predetermined type of microinstruction bit pattern for causing said store to return to a predetermined storage location within said store and wherein said control means includes; mode control means coupled to said logic means; reset switching means coupled to said logic means; and reset control means coupled to said reset switching means, said comparison means, said address register and to storage devices within said peripheral controller, said mode control means and said reset switching means when set in a first mode conditioning said reset control means to generate in response to said output signal a reset control signal for clearing said address register and said storage devices to an initial state and said reset control means being coupled to said gating means and operative at the termination of said reset control signal to condition said gating means for enabling of said controlling of said processing unit in accordance with the coding of said substitute microinstruction bit pattern as to have said controller proceed through the execution of a given microinstruction sequence in the same manner independent of the results of executing said sequence previously.
Claim 36
Dependent Claim
58 words
The controller of claim 32 wherein said reset switching means when set to a second mode inhibiting the operation of said reset control means and said gating means being operative to cause said store to cycle only between storage locations defined in accordance with said first plurality of switching means and said predetermined type of microinstruction bit pattern.
Claim 37
Dependent Claim
45 words
The system of claim 32 wherein said predetermined type of microinstruction bit pattern includes an op code field coded to specify an unconditional branch operation and a branch address field coded to designate the said predetermined storage location for defining a loop including said sequence.
Claim 38
Dependent Claim
101 words
The system of claim 32 wherein said controller further includes: a third plurality of switching means for generating address for designating a storage location used to synchronize the cycling of said read only store to an auxiliary device; comparator means coupled to said address register means and to said third plurality of switching means, said comparator means being operative to generate a control signal upon detecting a true comparison between said signals; and, output generating means coupled to said comparator means and operative to generate an output synchronizing pulse for said device in response to each occurrence of said control signal.
Claim 39
Dependent Claim
33 words
The system of claim 32 wherein said first plurality of switching means are set to designate a storage location having an address one less than the storage location storing the microinstruction being substituted.
Claim 40
Dependent Claim
91 words
The controller of claim 34 wherein said control unit further includes branch control means coupled to said address register and to receive said microinstruction word contents, said branch control means being responsive to predetermined type microinstruction words to perform testing of signals representative of the occurrence of different external and internal events indicated by the states of said storage devices, said branch control means being conditioned upon said clearing of said address register and said storage devices to sequence said control store through said loop each time in the same manner.
Claim 41
Dependent Claim
71 words
The controller of claim 37 wherein said control unit further includes: a plurality of return address registers individually coupled to said address register; an increment register individually coupled to said plurality of said return registers and to said address register aNd said reset control means generating a plurality of signals for conditioning each of said registers to be cleared to said initial state forcing said address register to a predetermined address.
Claim 42
Dependent Claim
17 words
The controller of claim 38 wherein said predetermined address is coded as an all zero address code.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-29 | 1979-03-31 | 1979-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-29 | 1983-03-31 | 1983-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-29 | 1987-03-31 | 1987-09-30 | $7700.00 | Window Closed / Lapsed |