Microprogrammed data processing system

Claim 2

A microprogrammed data processing system including: main data processing circuitry having bit storage positions which provide monitoring or control data for the system; and a selectively operable data forcing system comprising an injection register storing simulated monitoring or control data; connecting means for connecting bit storage positions of the injection register to respective ones of the bit storage positions of the main data processing circuitry, at least one of said bit storage positions of the main data processing circuitry being exclusively accessible by the data forcing system for entry of simulated monitoring or control data for the system; and identifying means responsive to the main data processing circuitry to identify a predetermined stage in the execution of a microprogram, said identifying means being adapted on identification of said predetermined stage to condition the connecting means to enter the contents of one or more of the bit storage positions of the injection register in said respective bit storage positions of the main data processing circuitry; thereby to initiate a particular system test or response deliberately other than by means of the microprogram.

Claim 3

A microprogrammed data processing system including: main data processing circuitry having bit storage positions which provide monitoring or control data for the system; and a selectively operable data forcing system comprising a plurality of injection registers storing simulated monitoring or control data; a plurality of connecting means each of which is for connecting bit storage positions of a respective one of the injection registers to respective ones of the bit storage positions of the main data processing circuitry; and identifying means responsive to the main data processing circuitry to identify a plurality of predetermined stages microprogram. the execution of a microprogram, said identifying means being adapted on identification of each of said predetermined stages to condition an appropriate one of the connecting means to enter the contents of one or more of the bit storage positions of its respective injection register in said respective bit storage positions of the main data processing circuitry; thereby to initiate a particular system test or response deliberately other than by means of the microprogram.

Claim 4

A microprogrammed data processing system including: main data processing circuitry having bit storage positions which provide monitoring or control data for the system; and a selectively operable data forcing system comprising a plurality of injection registers storing simulated monitoring or control data; a plurality of connecting means each of which is for connecting bit storage positions of a respective one of the injection registers to respective ones of the bit storage positions of the main data processing circuitry; and identifying means responsive to the main data processing circuitry to identify a plurality of predetermined stages microprogram. the execution of a microprogram, said identifying means being adapted on identification of each of said predetermined stages to condition an appropriate one of the connecting means to enter the contents of one or more of the bit storage positions of its respective injection register in said respective bit storage positions of the main data processing circuitry; thereby to initiate a particular system test or response deliberately other than by means of the microprogram.

Claim 5

A system as claimed in claim 2 wherein: the main data processing circuitry includes an operation retry means the working of which is initiated in response to a predetermined state of an indicating register; said indicating register forming at least part of the said bit storage positions of the main data processing circuitry into which said simulated data can be entered by the data forcing system.

Claim 6

A microprogrammed data processing system including: main data processing circuitry having bit storage positions which provide monitoring or control data for the system; and a selectively operable data forcing system comprising an injection register storing simulated erroneous monitoring or control data; connecting means for connecting bit storage positions of the injection register to respective ones of the bit storage positions of the main data processing circuitry; and identifying means responsive to the main data processing circuitry to identify a predetermined stage in the execution of a microprogram, said identifying means being adapted on identification of said predetermined stage to condition the connecting means to enter the contents of one or more of the bit storage positions of the injection register in said respective bit storage positions of the main data processing circuitry; thereby to initiate a particular system test or response deliberately other than by means of the microprogram.

Claim 7

A microprogrammed data processing system including: main data processing circuitry having bit storage positions which provide monitoring or control data for the system; and a selectively operable data forcing system comprising an injection register storing simulated erroneous monitoring or control data; connecting means for connecting bit storage positions of the injection register to respective ones of the bit storage positions of the main data processing circuitry; and identifying means responsive to the main data processing circuitry to identify a predetermined stage in the execution of a microprogram, said identifying means being adapted on identification of said predetermined stage to condition the connecting means to enter the contents of one or more of the bit storage positions of the injection register in said respective bit storage positions of the main data processing circuitry; thereby to initiate a particular system test or response deliberately other than by means of the microprogram.

Claim 8

A system as claimed in claim 4 in which at least one of said bit storage positions of the main data processing circuitry is exclusively accessible by the data forcing system for entry of simulated monitoring or control data for the system.

Claim 9

A microprogrammed data processing system including: main data processing circuiTry having bit storage positions which provide monitoring or control data for the system; and a selectively operable data forcing system comprising an injection register storing simulated monitoring or control data; connecting means for connecting bit storage positions of the injection register to respective ones of the bit storage positions of the main data processing circuitry; identifying means responsive to the main data processing circuitry to identify a predetermined stage in the execution of a microprogram, said identifying means being adapted on identification of said predetermined stage to condition the connecting means to enter the contents of one or more of the bit storage positions of the injection register in said respective bit storage positions of the main data processing circuitry; and presettable masking means for effectively masking selected bit storage positions of the injection register during entry of data from the injection register to the bit storage positions of the main data processing circuitry; thereby to initiate a particular system test or response deliberately other than by means of the microprogram.

Claim 10

A microprogrammed data processing system including: main data processing circuiTry having bit storage positions which provide monitoring or control data for the system; and a selectively operable data forcing system comprising an injection register storing simulated monitoring or control data; connecting means for connecting bit storage positions of the injection register to respective ones of the bit storage positions of the main data processing circuitry; identifying means responsive to the main data processing circuitry to identify a predetermined stage in the execution of a microprogram, said identifying means being adapted on identification of said predetermined stage to condition the connecting means to enter the contents of one or more of the bit storage positions of the injection register in said respective bit storage positions of the main data processing circuitry; and presettable masking means for effectively masking selected bit storage positions of the injection register during entry of data from the injection register to the bit storage positions of the main data processing circuitry; thereby to initiate a particular system test or response deliberately other than by means of the microprogram.

Claim 11

A system as claimed in claim 6 wherein: the main data processing circuitry includes an operation retry means the working of which is initiated in response to a predetermined state of an indicating register; said indicating register forming at least part of the said bit storage positions of the main data processing circuitry into which said simulated data can be entered by the data forcing system.

Claim 12

A system as claimed in claim 6 wherein: the data forcing system comprises; more than one said injection register, more than one said connecting means each of which is for connecting bit storage positions of a respective one of the injection registers to said respective bit storage positions of the main data processing circuitry; and identifying means responsive to the main data processing circuitry to identify a plurality of predetermined stages in the execution of a microprogram; said identifying means being adapted on identification of each of said predetermined stages to condition an appropriate one of said connecting means to enter the contents of one or more of the bit storage positions of its respective injection register into said respective bit storage positions of the main data processing circuitry.

Claim 13

A microprogrammed data processing system including: main data processing circuitry having bit storage positions which provide monitoring or control data for the system and having a count signal source operable to produce a count signal at predetermined intervals during the execution of a microprogram; and a selectively operable data forcing system comprising an injection register storing simulated monitoring or control data; connecting means for connecting bit storage positions of the injection register to respective ones of the bit storage positions of the main data processing circuitry; and identifying means responsive to the main data processing circuitry to identify a predetermined stage in the execution of a microprogram, said identifying means being adapted on identification of said predetermined stage to condition the connecting means to enter the contents of one or more of the bit storage positions of the injection register in said respective bit storage positions of the main data processing circuitry; said identifying means including a counter whose contents main altered by a fixed amount on receipt of each of said count signals, and counter testing means which tests the contents of the counter for a predetermined value microinstruction; which identifies said predetermined stage when the contents of the counter equal said predetermined value; thereby to initiate a particular system test or response deliberately other than by means of the microprogram.

Claim 14

A microprogrammed data processing system including: main data processing circuitry having bit storage positions which provide monitoring or control data for the system and having a count signal source operable to produce a count signal at predetermined intervals during the execution of a microprogram; and a selectively operable data forcing system comprising an injection register storing simulated monitoring or control data; connecting means for connecting bit storage positions of the injection register to respective ones of the bit storage positions of the main data processing circuitry; and identifying means responsive to the main data processing circuitry to identify a predetermined stage in the execution of a microprogram, said identifying means being adapted on identification of said predetermined stage to condition the connecting means to enter the contents of one or more of the bit storage positions of the injection register in said respective bit storage positions of the main data processing circuitry; said identifying means including a counter whose contents main altered by a fixed amount on receipt of each of said count signals, and counter testing means which tests the contents of the counter for a predetermined value microinstruction; which identifies said predetermined stage when the contents of the counter equal said predetermined value; thereby to initiate a particular system test or response deliberately other than by means of the microprogram.

Claim 15

A system as claimed in claim 9 wherein: the datA forcing system comprises; more than one said injection register, more than one said connecting means each of which is for connecting bit storage positions of a respective one of the injection registers to said respective bit storage positions of the main data processing circuitry, and identifying means responsive to the main data processing circuitry to identify a plurality of predetermined stages in the execution of a microprogram; said identifying means being adapted on identification of each of said predetermined stages to condition an appropriate one of said connecting means to enter the contents of one or more of the bit storage positions of its respective injection register into said respective bit storage positions of the main data processing circuitry.

Claim 16

A system as claimed in claim 9 wherein: the main data processing circuitry includes an operation retry means the working of which is initiated in response to a predetermined state of an indicating register; said indicating register forming at least part of the said bit storage positions of the main data processing circuitry into which said simulated data can be entered by the data forcing system.

Claim 17

A system as claimed in claim 9 further including: presettable masking means for effectively masking selected bit storage positions of the injection register during entry of data from the injection register to the bit storage positions of the main data processing circuitry.

Claim 18

A system as claimed in claim 14 wherein: the data forcing system comprises; more than one said injection register, more than one said connecting means each of which is for connecting bit storage positions of a respective one of the injection registers to said respective bit storage positions of the main data processing circuitry, and identifying means responsive to the main data processing circuitry to identify a plurality of predetermined stages in the execution of a microprogram; said identifying means being adapted on identification of each of said predetermined stages to condition an appropriate one of said connecting means to enter the contents of one or more of the bit storage positions of its respective injection register into said respective bit storage positions of the main data processing circuitry.

Claim 19

A system as claimed in claim 13 wherein: the main data processing circuitry includes an operation retry means the working of which is initiated in response to a predetermined state of an indicating register; said indicating register forming at least part of the said bit storage positions of the main data processing circuitry into which said simulated data can be entered by the data forcing system.

Claim 20

A microprogrammed data processing system including: main data processing circuitry having bit storage positions which provide monitoring or control data for the system and having an address register for containing the address of the current microinstruction; and a selectively operable data forcing system comprising an injection register storing simulated monitoring or control data; connecting means for connecting bit storage positions of the injection register to respective ones of the bit storage positions of the main data processing circuitry; and identifying means responsive to the main data processing circuitry to identify a predetermined stage in the execution of a microprogram, said identifying means being adapted on identification of said predetermined stage to condition the connecting means to enter the contents of one or more of the bit storage positions of the injection register in said respective bit storage positions of the main data processing circuitry; said identifying means including an address compare register, means for loading the address compare register with an address corresponding to said predetermined stage, and address comparison means operable to compare the contents of the address register foR equality with the contents of the address compare register to identify the said predetermined stage; thereby to initiate a particular system test or response deliberately other than by means of the microprogram.

Claim 21

A microprogrammed data processing system including: main data processing circuitry having bit storage positions which provide monitoring or control data for the system and having an address register for containing the address of the current microinstruction; and a selectively operable data forcing system comprising an injection register storing simulated monitoring or control data; connecting means for connecting bit storage positions of the injection register to respective ones of the bit storage positions of the main data processing circuitry; and identifying means responsive to the main data processing circuitry to identify a predetermined stage in the execution of a microprogram, said identifying means being adapted on identification of said predetermined stage to condition the connecting means to enter the contents of one or more of the bit storage positions of the injection register in said respective bit storage positions of the main data processing circuitry; said identifying means including an address compare register, means for loading the address compare register with an address corresponding to said predetermined stage, and address comparison means operable to compare the contents of the address register foR equality with the contents of the address compare register to identify the said predetermined stage; thereby to initiate a particular system test or response deliberately other than by means of the microprogram.

Claim 22

A system as claimed in claim 15 wherein: the data forcing system comprises; more than one said injection register, more than one said connecting means each of which is for connecting bit storage positions of a respective one of the injection registers to said respective bit storage positions of the main data processing circuitry, and identifying means responsive to the main data processing circuitry to identify a plurality of predetermined stages in the execution of a microprogram; said identifying means being adapted on identification of each of said predetermined stages to condition an appropriate one of said connecting means to enter the contents of one or more of the bit storage positions of its respective injection register into said respective bit storage positions of the main data processing circuitry.

Claim 23

A system as claimed in claim 15 wherein: the main data processing circuitry includes an operation retry means the working of which is initiated in response to a predetermined state of an indicating register; said indicating register forming at least part of the said bit storage positions of the main data processing circuitry into which said simulated data can be entered by the data forcing system.

Claim 24

A system as claimed in claim 15 further including: presettable masking means for effectively masking selected bit storage positions of the injection register during entry of data from the injection register to the bit storage positions of the main data processing circuitry.

Claim 25

A system as claimed in claim 18 wherein: the data forcing system comprises; more than one said injection register, more than one said connecting means each of which is for connecting bit storage positions of a respective one of the injection registers to said respective bit storage positions of the main processing circuitry; and identifying means responsive to the main data processing circuitry to identify a plurality of predetermined stages in the execution of a microprogram; said identifying means being adapted on identification of each of said predetermined stages to condition an appropriate one of said connecting means to enter the contents of one or more of the bit storage positions of its respective injection register into said respective bit storage positions of the main data processing circuitry.

Claim 26

A system as claimed in claim 19 wherein: the main data processing circuitry includes an operation retry means the working of which is initiated in response to a predetermined state of an indicating register; said indicating register forming at least part of the said bit storage positions of the main data processing circuitry into which said simulated data can be entered by the data forcing system.