Diagnostic checking apparatus

Claim 2

Diagnostic Apparatus for locating any one of a plurality of program instructions of a program stored within an addressable memory of a data processing system which includes control cycle means for generating control signals required for processing said instructions, said diagnostic apparatus comprising: means for receiving a first set of binary coded signals corresponding to a predetermined portion of each instruction read out from said memory during the processing of said instruction, said predetermined portion defining a type of operation to be performed by said system; switching means for generating a second set of binary coded signals identifying a type of instruction to be located; and, comparison means coupled to said control cycle means and including first and second sets of input terminals and an output terminal, said first set of input terminals being coupled to receive said first set of binary coded signals and said second set of input terminals being coupled to receive said second set of binary coded signals and said output terminal being coupled to said control cycle means, said comparison means being conditioned by said control means to compare said codes during the processing of said instruction and said comparison means further including means operative to generate a control signal at said output terminal upon sensing a true comparison between said codes, said control cycle means being conditioned by said control signal to bring said system to an orderly halt.

Claim 3

The apparatus of claim 1 wherein said means for receiving includes storage register means coupled to said memory for storing a command code of each said instruction and wherein said control cycle means includes detector circuit means coupled to said storage register means and to said output terminal, said detector means being operative upon sensing when an instruction includes an illegal command code to condition said control cycle means to complete the processing of an instruction by bringing said system to an orderly halt, said comparison means being operative to condition detector circuit means upon sensing said true comparison to operate as having sensed an illegal command code.

Claim 4

The system of claim 1 wherein said switching means includes a plurality of manually controlled switch circuit means for generating said second set of binary coded signals.

Claim 5

A data processing system including; a main memory for storing program instructions and data, storage register means coupled to said memory for storing a first binary code corresponding to a predetermined portion of a program instruction to be executed by said system, detector circuit means coupled to said register means for signalling when said binary code specifies a nonexecutable instruction, control circuit means coupled to said storage register mean and to said detector circuit means, said control means being conditioned by said code to generate a plurality of subcommand signals for directing said system in executing those operations specified by said program instruction, mode control means coupled to said control circuit means, said mode control means being operative to establish a number of different test modes for said system; and, said system further including diagnostic apparatus comprising: storage register coupled to said storage register means and to said mode control means; input switching means for generating signals representative of a second binary code; and, comparison circuit means coupled to said storage register means to said mode control means and to said input switching means, said comparison means being conditioned by said mode control means to generate an output signal upon sensing a true comparison between said first and second binary codes, said detector circuit means being operative in response to said output signal to condition said control means to bring said system to an orderly halt when said mode control means has conditioned said system to operate in a predetermined one of said modes.

Claim 6

A data processing system including; a main memory for storing program instructions and data, storage register means coupled to said memory for storing a first binary code corresponding to a predetermined portion of a program instruction to be executed by said system, detector circuit means coupled to said register means for signalling when said binary code specifies a nonexecutable instruction, control circuit means coupled to said storage register mean and to said detector circuit means, said control means being conditioned by said code to generate a plurality of subcommand signals for directing said system in executing those operations specified by said program instruction, mode control means coupled to said control circuit means, said mode control means being operative to establish a number of different test modes for said system; and, said system further including diagnostic apparatus comprising: storage register coupled to said storage register means and to said mode control means; input switching means for generating signals representative of a second binary code; and, comparison circuit means coupled to said storage register means to said mode control means and to said input switching means, said comparison means being conditioned by said mode control means to generate an output signal upon sensing a true comparison between said first and second binary codes, said detector circuit means being operative in response to said output signal to condition said control means to bring said system to an orderly halt when said mode control means has conditioned said system to operate in a predetermined one of said modes.

Claim 7

The system of claim 4 wherein said input switching means includes a plurality of manually controlled switch circuit means for generating signals corresponding to said second binary code.

Claim 8

The system of claim 4 wherein said mode control means includes: a plurality of bistable storage means, each individually coupled to said diagnostic apparatus and decoder means individually coupled to each of said plurality of bistable storage means, said decoder means being operative to apply a predetermined set of signals for switching a predetermined one of said plurality of bistable storage means from a first state to a second state, establishing said predetermined one of said number of test modes for said system.

Claim 9

The system of claim 6 wherein said system is conditioned by said mode control means to process program instructions at normal operating speeds when system is operating in said predetermined one of said operating modes.

Claim 10

The system of claim 4 wherein said comparison means includes: arithmetic and logic circuit means, said arithmetic and logic circuit means having first and second sets of input terminals and an output terminal, said first set of input terminals being coupled to receive said first binary code and said second set of input terminals being coupled to receive said second binary code and said output terminal being coupled to said detector circuit means, said arithmetic and logic circuit means being conditioned to perform a subtract operation upon said binary codes applied to said first and second input terminals and generate said output signal when said codes match.

Claim 11

The system of claim 4 wherein said system further includes error control means coupled to said detector circuit means, said error control means being conditioned by said detector circuit means to generate a signal indicating an error condition upon said system being brought to said orderly halt.

Claim 12

The system of claim 9 wherein said error control means includes first and second series connected bistable means, said first bistable means being coupled to said mode control means, said bistable means being conditioned by said mode control means to be switched from a first to a second state in response to said output signal, said first bistable means when in said second state being operative to condition said control means to bring said system to said orderly halt and place said system in an abnormal stop condition and said first bistable means conditioning said second bistable means to switch from a first to a second state in response to a clear control signal, said second bistable means when in said second stage being operative to place said system in a normal stop condition.

Claim 13

In a data processing system including; an addressable memory including a plurality of storage locations for storing program instructions and data, address register means coupled to said memory for storing an address of a storage location to be referenced, register means coupled to said memory for storing the contents of a referenced storage location, an addressable control memory including a plurality of storage locations for storing information used in processing the instructions of a program, one of said plurality of storage locations being arranged to store address information signals identifying the storage location in said memory which stores a first portion of a next instruction to be processed, op-code register means coupled to said register means for storing bit pattern corresponding to the op-code of an instruction being processed, illegal op-code detector circuit means coupled to said op-code register means for signalling the presence of an illegal bit pattern in said op-code register, control sequencing means coupled to said op-code register means and to said illegal op-code detector circuit means, said control sequencing means being operative to generate control signals for the different cycles of operation executed by said system in extraction and execution of each program instrucTion, and diagnostic apparatus comprising: mode control switching means coupled to said control sequencing means and operative to establish a plurality of test modes for said system, said mode control switching means being set to establish a predetermined one of said modes; input switching means for generating a bit pattern identifying the op-code of a predetermined type of program instruction; comparison means coupled to said mode control switch-in means and including first and second sets of input terminals and an output terminal, said first set of input terminals being coupled to receive said bit pattern from said op-code register means, and said second set of input terminals being coupled to receive said bit pattern from said input switching means, said comparison being conditioned by said mode switching means to compare said bit patterns during a predetermined cycle of operation and said comparison means including means operative to generate a control signal at said output terminal in response to a true comparison, said illegal op-code detector means being operative in response to said control signal to treat said op-code bit pattern as illegal when said system is being operated in said predetermined mode and condition said control sequencing means to halt the processing of said instruction at a point where said one of said plurality of control memory storage locations stores address information signals which identifies the storage location in said memory which stores said op-code bit pattern.

Claim 14

In a data processing system including; an addressable memory including a plurality of storage locations for storing program instructions and data, address register means coupled to said memory for storing an address of a storage location to be referenced, register means coupled to said memory for storing the contents of a referenced storage location, an addressable control memory including a plurality of storage locations for storing information used in processing the instructions of a program, one of said plurality of storage locations being arranged to store address information signals identifying the storage location in said memory which stores a first portion of a next instruction to be processed, op-code register means coupled to said register means for storing bit pattern corresponding to the op-code of an instruction being processed, illegal op-code detector circuit means coupled to said op-code register means for signalling the presence of an illegal bit pattern in said op-code register, control sequencing means coupled to said op-code register means and to said illegal op-code detector circuit means, said control sequencing means being operative to generate control signals for the different cycles of operation executed by said system in extraction and execution of each program instrucTion, and diagnostic apparatus comprising: mode control switching means coupled to said control sequencing means and operative to establish a plurality of test modes for said system, said mode control switching means being set to establish a predetermined one of said modes; input switching means for generating a bit pattern identifying the op-code of a predetermined type of program instruction; comparison means coupled to said mode control switch-in means and including first and second sets of input terminals and an output terminal, said first set of input terminals being coupled to receive said bit pattern from said op-code register means, and said second set of input terminals being coupled to receive said bit pattern from said input switching means, said comparison being conditioned by said mode switching means to compare said bit patterns during a predetermined cycle of operation and said comparison means including means operative to generate a control signal at said output terminal in response to a true comparison, said illegal op-code detector means being operative in response to said control signal to treat said op-code bit pattern as illegal when said system is being operated in said predetermined mode and condition said control sequencing means to halt the processing of said instruction at a point where said one of said plurality of control memory storage locations stores address information signals which identifies the storage location in said memory which stores said op-code bit pattern.

Claim 15

The system of claim 11 wherein said input switching means includes a plurality of manually controlled switch circuit means for generating said op-code bit pattern.

Claim 16

The system of claim 11 wherein said comparison means includes: arithmetic and logic circuit means, said arithmetic and logic circuit means having first and second sets of input terminals and an output terminal, said first set of input terminals being coupled to receive said first binary code and said second set of input terminals being coupled to receive said second binary code and said output terminal being coupled to said detector circuit means, said arithmetic and logic circuit means being conditioned to perform a subtract operation upon said binary codes applied to said first and second input terminals and generate said output signal when said codes match.

Claim 17

The system of claim 11 wherein said system further includes error control means coupled to said illegal detector circuit means, said error control means being conditioned by said detector circuit means to generate signal indicating an error condition upon said halt.

Claim 18

The system of claim 14 wherein said error control means includes first and second series connected bistable means, said first bistable means being coupled to said mode control means, said bistable means being conditioned by said mode control means to be switched from a first to a second state in response to said output signal, said first bistable means when in said second state being operative to condition said control means to bring said system to said orderly halt and place said system in an abnormal stop condition and said first bistable means conditioning said second bistable means to switch from a first to a second state in response to a clear control signal, said second bistable means when in said second state being operative to place said system in a normal stop condition.

Claim 19

Testing apparatus in combination with a data processing system for selectively locating any one of a plurality of program instructions of a program stored within an addressable memory during the processing instructions by said data processing system directed by control means included in said system, said testing apparatus comprising: storage means coupled to receive a first set of binary coded signals corresponding to a command code of each instruction during a predetermined interval of a period of time allocated in processing said each instruction; switching meaNs connected to generate a second set of binary coded signals identifying a type of instruction to be located; and, comparison means, said comparison means being coupled to receive said first and second set of binary coded signals, said comparison means including means operative to generate a control signal upon said comparison means sensing a true comparison between said codes, said control means being conditioned by said control signal to bring said system to an orderly halt.

Claim 20

Testing apparatus in combination with a data processing system for selectively locating any one of a plurality of program instructions of a program stored within an addressable memory during the processing instructions by said data processing system directed by control means included in said system, said testing apparatus comprising: storage means coupled to receive a first set of binary coded signals corresponding to a command code of each instruction during a predetermined interval of a period of time allocated in processing said each instruction; switching meaNs connected to generate a second set of binary coded signals identifying a type of instruction to be located; and, comparison means, said comparison means being coupled to receive said first and second set of binary coded signals, said comparison means including means operative to generate a control signal upon said comparison means sensing a true comparison between said codes, said control means being conditioned by said control signal to bring said system to an orderly halt.

Claim 21

The apparatus of claim 16 wherein said control means includes detector circuit means for sensing an illegal command code, said detector means being coupled to receive said first set of binary coded signals and including means coupled to said comparison means, said means being operative in response to said control signal to condition said detector circuit means to operate as having sensed an illegal command code by initiating said orderly halt.

Claim 22

The apparatus of claim 16 wherein said switching means includes a plurality of manually controlled switch circuit means for generating said second set of binary coded signals.

Claim 23

The apparatus of claim 16 wherein said comparison means includes: arithmetic and logic circuit means, said arithmetic and logic circuit means having first and second sets of input terminals and an output terminal, said first set of input terminals being coupled to receive said first binary code and said second set of input terminals being coupled to receive said second binary code and said output terminal being coupled to said detector circuit means, said arithmetic and logic circuit means being conditioned to perform a subtract operation upon said binary codes applied to said first and second input terminals and generate said output signal when said codes match.

Claim 24

The apparatus of claim 16 wherein said system further includes error control means coupled to said detector circuit means, said error control means being conditioned by said detector circuit means to general s signal indicating an error condition upon said system being brought to said orderly halt.

Claim 25

The apparatus of claim 20 wherein said error control means includes first and second series connected bistable means, said first bistable means being coupled to said mode control means, said bistable means being conditioned by said mode control means to be switched from a first to a second state in response to said output signal, said first bistable means when in said second state being operative to condition said control means to bring said system to said orderly halt and place said system in an abnormal stop condition and said first bistable means conditioning said second bistable means to switch from a first to a second state in response to a clear control signal, said second bistable means when in said second state being operative to place said system in a normal stop condition.