Synchronous multi-processor system utilizing a single external memory unit

Claim 1

In a computing system having a single external memory, the combination comprising: a. first and second central processing units, each processor formed on a single chip of semiconductor material, each processor characterized by An operating cycle that includes a first portion only during which the processor can access a selected portion of said external memory and a second portion during which data is operated on by the CPU, each CPU having an accumulator register for storing the result of data operation; b. means operably connected to said first and second processing units for synchronizing operation thereof such that said first portion of said first processor operating cycle occurs only simultaneously with said second portion of said second processor operating cycle; said means for synchronizing including i. switching means for setting one processor to a wait condition is response to a first input signal selecting said one processor for access to said external memory, ii. detector means coupling said first and second processors operable to provide an enabling signal to said other processor in response to said one processor switching to the wait mode and iii. logic means responsive to the termination of the first portion of the operating cycle of said other processor operative to enable said one processor to a ready state during the second portion of the operating cycle of said other processor; and c. interface circuitry operably connected to first and second processors for selectively coupling external inputs to said processors and for providing system outputs.

Claim 7

A method for operating a fully synchronous computing system that includes an external memory shared by first and second central processing units each having an operating cycle characterized by a first portion only during which the processor can access said memory and a second portion during which the processor operates upon the data received during the first portion, said processors and memory respectively being interconnected by a common parallel buss, comprising the steps of: a. generating synchronizing signals in said first and second processing units corresponding to initiation of said first and second operating cycle portions thereof respectively; and generating logic enable signals responsive to said synchronizing signals for coupling said first processing unit to said external memory only during said second operating cycle portion of said second processing unit, and for coupling said second processing unit to said external memory only during said second operating cycle portion of said first processing unit, said step of generating logic enable signals including switching said first processor to a wait mode of operation in response to an external signal selecting said second processor for memory access, detecting when said first processor enters said wait mode and providng an enable signal to said second preocessor enabling it to effect the first portion of its operating cycle to retrieve data from memory to execute a first program, detecting the termination of said first portion of said operating cycle, and applying an enable signal to said first processor to enable it to operate during the first portion of its operating cyCle in order to access said memory to execute a second program, said first processor accessing memory simultaneously with said second processor operating on the data it retrieved during the previous portion of its operating cycle.

Claim 8

A method for operating a fully synchronous computing system that includes an external memory shared by first and second central processing units each having an operating cycle characterized by a first portion only during which the processor can access said memory and a second portion during which the processor operates upon the data received during the first portion, said processors and memory respectively being interconnected by a common parallel buss, comprising the steps of: a. generating synchronizing signals in said first and second processing units corresponding to initiation of said first and second operating cycle portions thereof respectively; and generating logic enable signals responsive to said synchronizing signals for coupling said first processing unit to said external memory only during said second operating cycle portion of said second processing unit, and for coupling said second processing unit to said external memory only during said second operating cycle portion of said first processing unit, said step of generating logic enable signals including switching said first processor to a wait mode of operation in response to an external signal selecting said second processor for memory access, detecting when said first processor enters said wait mode and providng an enable signal to said second preocessor enabling it to effect the first portion of its operating cycle to retrieve data from memory to execute a first program, detecting the termination of said first portion of said operating cycle, and applying an enable signal to said first processor to enable it to operate during the first portion of its operating cyCle in order to access said memory to execute a second program, said first processor accessing memory simultaneously with said second processor operating on the data it retrieved during the previous portion of its operating cycle.