Automatic context switching in a multiprogrammed multiprocessor system

Claim 3

The combination set forth in claim 1 wherein means are provided in said central processing unit to enable said peripheral processing unit to respond to said first signal or second signal only after a predetermined delay following generation thereof.

Claim 4

The combination set forth in claim 1 wherein circuit means applies error signals produced in said central processing unit to said peripheral processing unit to switch said central processing unit from said current program to said next program.

Claim 5

The combination set forth in claim 3 wherein said error signal is logically routed in said peripheral processor over the same path as said second signal.

Claim 6

A digital data processor having a memory, an arithmetic unit, a central processing unit for processing multiprograms, a peripheral processing unit, memory storing multiprograms as they await execution while a current program is in process in said central processing unit and said memory having a reserved storage address, the combination which comprises: a. an instruction storage register through which instructions pass in transit to said arithmetic unit, said instructions including a particular control code, b. decode means in said central processing unit having two output lines and coupled to said register for response to a particular control code forming a part of said instructions to produce an output control signal on a first of said lines when said control code represents a system call-and-proceed command and on a second said line when said code represents a system call-and-wait command, c. control means including memory responsive channel leading to said central processing unit to enable application of said control output signal to said arithmetic unit if said reserved memory address is available, d. address generating means in said central processing unit normally producing a control code to control storing and fetching of operands between memory and said arithmetic unit, and e. means responsive to said output control signal for directing to said reserved address said control code in substitution of said operands.

Claim 7

A digital data processor having a memory, an arithmetic unit, a central processing unit for processing multiprograms, a peripheral processing unit, memory storing multiprograms as they await execution while a current program is in process in said central processing unit and said memory having a reserved storage address, the combination which comprises: a. an instruction storage register through which instructions pass in transit to said arithmetic unit, said instructions including a particular control code, b. decode means in said central processing unit having two output lines and coupled to said register for response to a particular control code forming a part of said instructions to produce an output control signal on a first of said lines when said control code represents a system call-and-proceed command and on a second said line when said code represents a system call-and-wait command, c. control means including memory responsive channel leading to said central processing unit to enable application of said control output signal to said arithmetic unit if said reserved memory address is available, d. address generating means in said central processing unit normally producing a control code to control storing and fetching of operands between memory and said arithmetic unit, and e. means responsive to said output control signal for directing to said reserved address said control code in substitution of said operands.

Claim 8

The combination set forth in claim 5 wherein a fixed address storage coded to said reserved memory address is provided in said central processing unit and wherein a gate responsive to said output signal routes said control code to memory at said particular address.

Claim 9

The processor of claim 5 wherein: e. interface logic in said peripheral processing unit has fixed path connections to said central processing unit including said lines, f. a path for applying at least one enabling signal from said central processing unit to said peripheral processing unit, and g. fixed lines to a memory control for enabling application of said output signal to said arithmetic unit.

Claim 10

In a multiprogrammed multiprocessor digital data processing system comprising a central processing unit, a peripheral processing unit and a common memory unit, a method of performing automatic context switching which comprises: a. in response to the execution of a system call and wait instruction or upon occurrence of a program error, applying a control signal from said central processing unit to said peripheral processing unit; b. transferring from said central processing unit to said memory unit a code indicative of the status of said central processing unit; and c. switching into said central processing unit a different status so that it caN proceed with execution of a different program, said different program having been priority selected in advance by said peripheral processing unit.

Claim 11

In a multiprogrammed multiprocessor digital data processing system comprising a central processing unit, a peripheral processing unit and a common memory unit, a method of performing automatic context switching which comprises: a. in response to the execution of a system call and wait instruction or upon occurrence of a program error, applying a control signal from said central processing unit to said peripheral processing unit; b. transferring from said central processing unit to said memory unit a code indicative of the status of said central processing unit; and c. switching into said central processing unit a different status so that it caN proceed with execution of a different program, said different program having been priority selected in advance by said peripheral processing unit.

Claim 12

The method according to claim 8 further comprising storing a code in a reserved cell in said memory and transferring said code to said peripheral processor, said code directing said peripheral processor to perform input-output functions.