Common storage controller for dual processor system

Claim 2

A digital data processing system comprising in combination: a. first and second central processor units; b. first and second memory banks coupled to said first and second central processor units respectively, for storing information at addressable locations therein, 1. said first and second memory banks each having substantially identical cycle timeS and a predetermined range of addresses therein set aside for storing identical information; c. first and second controller means connected intermediate said first central processor unit and said first memory bank and said second central processor unit and said second memory bank, respectively, said first controller means including, 1. means for detecting when said first central processor unit is writing new information into said first memory bank at an address within said predetermined range of addresses, and 2. means responsive to said detecting means for transferring said new information and said address to said second controller means for causing the same new information to be stored at said address in said range of addresses in said second memory bank.

Claim 3

means responsive to said detecting means for transferring said new information and said address to said second controller means for causing the same new information to be stored at said address in said range of addresses in said second memory bank.

Claim 4

means responsive to said detecting means for transferring said new information and said address to said second controller means for causing the same new information to be stored at said address in said range of addresses in said second memory bank.

Claim 5

A dual processor computing system comprising in combination: a. first and second central processor units; b. peripheral storage devices for storing a data base connected to said first and second central processors for supplying information thereto and receiving information therefrom; c. a first memory bank coupled to said first central processor unit by a first common storage controller and a second memory bank coupled to said second central processor unit by a second common storage controller,

Claim 6

A dual processor computing system comprising in combination: a. first and second central processor units; b. peripheral storage devices for storing a data base connected to said first and second central processors for supplying information thereto and receiving information therefrom; c. a first memory bank coupled to said first central processor unit by a first common storage controller and a second memory bank coupled to said second central processor unit by a second common storage controller,

Claim 7

said first and second memory storing operands and instructions, including replace class instructions, at addressable locations therein including said predetermined range of addresses, and

Claim 8

said first and second memory storing operands and instructions, including replace class instructions, at addressable locations therein including said predetermined range of addresses, and

Claim 9

said first and second controller devices being bidirectionally coupled together by address lines, data lines and control lines.

Claim 10

said first and second controller devices being bidirectionally coupled together by address lines, data lines and control lines.

Claim 11

The system as in claim 2 wherein said first and second common storage controllers further include acknowledge control means for returning an acknowledge control signal to the processor unit originating said write request control signal upon the completion of the storage of said write data within said predetermined range of addresses in both of said first and second memory banks.

Claim 12

The system as in claim 2 wherein each of said common storage controllers further include priority means for determining the order in which write requests originating at one of said processor units or received from the other of said common storage controllers will be honored.

Claim 13

The system as in claim 4 wherein said priority means in said common storage controllers is preconditioned to receive a request control signal from its associated central processor unit during each memory cycle.

Claim 14

Digital controller means for interconnecting at least two central processor units, each with its own associated memory bank for ensuring that information stored in a predetermined range of addresses in the memory bank associated with a first central processor unit will also be stored in the same predetermined range of addresses in the memory bank associated with the second central processor unit, comprising in combination: a. address selector means adapted to receive address representing signals originating at one or the other of said two central processor units for selectively routing said address representing siGnals to each of said memory banks; b. write data selector means adapted to receive write data representing signals originating at one or the other of said two central processor units and to selectively transfer said write data to a memory bank location determined by said address representing signals; c. comparing means connected to receive said address representing signals for comparing said address representing signals with a predetermined boundary address and for producing a control signal when said address representing signals define an address within said predetermined range of addresses; and d. control means responsive to said control signal for enabling said write data selector means and said address selector means to transfer the address representing signals and data representing signals to the memory bank associated with the central processor unit other than the one originating said address representing signals and data representing signals.

Claim 15

Digital controller means for interconnecting at least two central processor units, each with its own associated memory bank for ensuring that information stored in a predetermined range of addresses in the memory bank associated with a first central processor unit will also be stored in the same predetermined range of addresses in the memory bank associated with the second central processor unit, comprising in combination: a. address selector means adapted to receive address representing signals originating at one or the other of said two central processor units for selectively routing said address representing siGnals to each of said memory banks; b. write data selector means adapted to receive write data representing signals originating at one or the other of said two central processor units and to selectively transfer said write data to a memory bank location determined by said address representing signals; c. comparing means connected to receive said address representing signals for comparing said address representing signals with a predetermined boundary address and for producing a control signal when said address representing signals define an address within said predetermined range of addresses; and d. control means responsive to said control signal for enabling said write data selector means and said address selector means to transfer the address representing signals and data representing signals to the memory bank associated with the central processor unit other than the one originating said address representing signals and data representing signals.

Claim 16

The digital controller as in claim 6 and further including acknowledge control means for signaling the central processor means originating said address representing signals that said write data has been stored in said predetermined range of addresses in both of said memory banks.

Claim 17

In a dual processor data processing system wherein first and second processors, each with its own associated memory bank, are capable of sharing a common data base stored in a shared peripheral mass storage unit the combination comprising: a. a first central processor unit coupled to a first memory bank by a first controller device; b. a second central processor unit coupled to a second memory bank by a second controller device,

Claim 18

In a dual processor data processing system wherein first and second processors, each with its own associated memory bank, are capable of sharing a common data base stored in a shared peripheral mass storage unit the combination comprising: a. a first central processor unit coupled to a first memory bank by a first controller device; b. a second central processor unit coupled to a second memory bank by a second controller device,

Claim 19

The system as in claim 8 wherein said first and second controller devices each include: a. first gating means connected intermediate said address lines and said first and second memory banks and connected to receive address representing signals from its associated central processor unit and, when enabled, will convey said address representing signals to each of said memory banks; b. second gating means connected intermediate said data lines and said first and second memory banks and connected to receive write data signals from its associated central processor unit and, when enabled, will convey said write data signals to each of said memory banks at locations established by said address representing signals; and c. control means including timing means responsive to write request control signals originated at said first or second central processor unit for enabling said first and second gating means in sequence.

Claim 20

The system as in claim 9 and further including: a. third gating means connected intermediate said control lines and said first and second memory banks and said first and second central processor units and, when enabled, will convey acknowledge control signals from said memory banks to the central processor unit originating said address representing signals following the entry of said write data signals into each of said storage banks.

Claim 21

The system as in claim 9 wherein each of said first and second controller devices further include: a. priority control means connected to receive request control signals from its associated central processor unit and from the other of said controller devices for establishing the order in which said request control signals arE to be honored by said memory banks.

Claim 22

The system as in claim 11 and further including: a. comparator means connected to receive said address representing signals from its associated central processor unit for generating a control signal when the received address lies within said predetermined range of addresses; b. lockout control means responsive to said control signal generated by said comparator means and to a signal from said associated central processor unit produced when said associated central processor unit is executing a replace class instruction for generating a replace lockout control signal; c. means for applying said replace lockout control signal to said third gating means for inhibiting said third gating means until both cycles of said replace class instruction have been completed; and d. means for applying said replace lockout control signal to said priority control means to inhibit said priority control means from honoring further requests from said other controller device until said third gating means is enabled.