Abstract The digital communication interface facilitates the transfer of blocks of data between the memories of two computers and provides for maximum data density of information storage when the two computers involved have different word sizes. Once initialized, the interface transfers data via cycle-steal with respect to the two computers'' memories. Either computer may detect the status of the interface at any time during a data transfer and can halt or modify the operation as desired. When a transfer operation has been completed, the interface can signal either or both computers. The interface includes a data register which is divided into two sections. The number of bits in each section corresponds to the number of bits in the memory word of each of the two computers. Thus, if the two computers have different word sizes, the two sections of the data register will have different lengths. The data register is a circular bidirectional shift register which provides a parallel-to-serial-to-parallel data path. The operation of the interface during data-transfers is completely controlled by registers internal to itself which can be loaded by either computer. The condition of the data-handling circuits is indicated at all times by these registers which can also be read by either computer. This allows the interface to be commanded fully by either computer or by both. The control registers are capable of controlling the unit size of contiguous groups of data words transferred between the memories of the two computers such that the unit size may be either the least common multiple of the word size of each of the two computers or the smaller of the two word sizes. In the latter case a word-for-word relationship is maintained, whereas this is not true in the former case. The former case, however, permits high-density packing of the data from the memory of one computer to the memory of the second computer. The control registers are also capable of independently varying the effective length of each section of the data register. This permits data from one section to be introduced into the other at any bit position.
A digital communication interface to facilitate the transfer of blocks of data between the memories of a first data processor and a second data processor, said first processor having a word length of m bits and said second processor having a word length of n bits, said interface comprising: a data register having first and second sections, said first section being in communication with the memory of said first processor for transferring therebetween in parallel a data word m bits or less in length, said second section being in communication with the memory of said second processor for transferring therebetween in parallel a data word n bits or less in length, independently of the transfer of a transfer of a data word to or from said first section, and control means for serially shifting the contents of said first section into said second section at a selected bit position thereof and the contents of said second section into said first section a selected bit position thereof whereby the effective lengths of the data words transferred between the two processor can be independently varied.
Claim 2
Dependent Claim
183 words
A digital communication interface to facilitate the transfer of blocks of data between the memories of a first data processor and a second data processor, said first processor having a word length of m bits and said second processor having a word length of n bits, said interface comprising: a data register having first and second sections, said first section being in communication with the memory of said first processor for transferring therebetween in parallel a data word m bits or less in length, said second section being in communication with the memory of said second processor for transferring therebetween in parallel a data word n bits or less in length, independently of the transfer of a transfer of a data word to or from said first section, and control means for serially shifting the contents of said first section into said second section at a selected bit position thereof and the contents of said second section into said first section a selected bit position thereof whereby the effective lengths of the data words transferred between the two processor can be independently varied.
Claim 3
Dependent Claim
237 words
A digital communication interface as recited in claim 1 wherein said control means comprises: first shift count means for counting the number of shifts of data in said first section of said data register and stopping the shifting of said data register at a first predetermined count to enable data to be transferred in parallel between said first section and said first processor, first frame size register means for presetting said first shift count means with a first number corresponding to the size word to be transferred between said first section and said first processor each time said first shift count means counts to said first predetermined number, second shift count means for counting the number of shifts of the data in said second section of said data register and stopping the shifting of said data register at a second predetermined count to enable data to be transferred in parallel between said second section and said second processor, second frame size register means for presetting said second shift count means with a second number corresponding to the size of the word to be transferred between said second section and said second processor each time said second shift count means counts to said second predetermined number, and logic means responsive to said first and second frame size registers for selecting the bit positions in said first and second sections of the data register into which data is shifted.
Claim 4
Dependent Claim
35 words
A digital communication interface as recited in claim 2 wherein said first and second predetermined counts are zero and wherein said first number is m or less and said second number is n or less.
Claim 5
Dependent Claim
27 words
A digital communication interface as recited in claim 2 wherein said first and second frame size register means are directly addressable by said first and second processors.