US3883801A
Expired / Lapsed
US
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Fault testing of logic circuits
Assignee: AT&T Inc
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Filing: 1973-11-07
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Granted: 1975-05-13
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Expires: 1993-11-07
Abstract
Abstract A method and apparatus for detecting faults in logic circuits requires the retention of a single binary reference word for each circuit type to be tested. Responsive to a sequence of input binary words preselected to reveal potential faults of the circuit under test, a single binary word is derived, as a figure of merit, by adding the sequence of output binary words produced by the circuit under test. Comparison of the single binary word generated by the circuit under test with the reference binary word which is characteristic of a properly functioning circuit of the same type provides the desired fault indication. Economies of time and apparatus are thus realized.
Inventors
- 👤 Garry Carson Hess
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 23:39
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/277
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
120 words
A logic circuit tester of the type in which a sequence of input vectors activates a logic circuit under test to yield a corresponding sequence of output vectors, said tester comprising: an accumulator for summing the sequence of output vectors from the logic circuit under test into a single characterizing test sum vector, means for adding the overflow bit of said accumulator to the least significant input bit thereof, a reference source providing a reference sum vector characterizing a properly functioning logic circuit of the type under test, and a comparator responsive jointly to the respective test and reference sum vectors for indicating the state of correspondence thereof and hence the state of operativeness of the logic circuit under test.
Claim 2
Dependent Claim
120 words
A logic circuit tester of the type in which a sequence of input vectors activates a logic circuit under test to yield a corresponding sequence of output vectors, said tester comprising: an accumulator for summing the sequence of output vectors from the logic circuit under test into a single characterizing test sum vector, means for adding the overflow bit of said accumulator to the least significant input bit thereof, a reference source providing a reference sum vector characterizing a properly functioning logic circuit of the type under test, and a comparator responsive jointly to the respective test and reference sum vectors for indicating the state of correspondence thereof and hence the state of operativeness of the logic circuit under test.
Claim 3
Dependent Claim
99 words
In a tester for logic circuits the method of detecting faults in the logic circuits comprising the steps of: applying a predetermined input test sequence to said logic circuit, adding the corresponding sequence of output signals from said logic circuit to obtain a single test sum signal, adding carries from the most significant bit of said single test sum signal to the sequence of output signals at the least significant bit thereof, and testing for the correspondence of the single test sum signal with a predetermined reference sum signal characteristic of a fault-free logic circuit of the same type.
Claim 4
Dependent Claim
99 words
In a tester for logic circuits the method of detecting faults in the logic circuits comprising the steps of: applying a predetermined input test sequence to said logic circuit, adding the corresponding sequence of output signals from said logic circuit to obtain a single test sum signal, adding carries from the most significant bit of said single test sum signal to the sequence of output signals at the least significant bit thereof, and testing for the correspondence of the single test sum signal with a predetermined reference sum signal characteristic of a fault-free logic circuit of the same type.
Claim 5
Dependent Claim
74 words
The logic circuit tester of claim 1 further comprising a plurality of interchangeable interface matrices, each one employed with a different type of logic circuit, each of said matrices comprising: means for applying a predetermined number of bits of the vectors of said input sequence to the inputs of said logic circuit, means for applying the sequence of output vectors to said accumulator, and means for applying said reference sum vector to said comparator.
Claim 6
Dependent Claim
55 words
The logic circuit tester of claim 1 further comprising a single interface matrix useful for self-testing said tester, said interface matrix comprising: means for applying said sequence of input vectors directly to said accumulator, and means for applying to said comparator a reference sum vector equal to the sum of said sequence of input vectors.
Claim 7
Dependent Claim
72 words
In a logic circuit tester of the type in which a sequence of input vectors activates a logic circuit under test to yield a corresponding sequence of output vectors, said tester including means for combining said sequence of output vectors into a single characterizing test sum vector, the improvement comprising: means for adding the most significant output bit of said combining means to the least significant bits of said output vector sequence.
Claim 8
Dependent Claim
72 words
In a logic circuit tester of the type in which a sequence of input vectors activates a logic circuit under test to yield a corresponding sequence of output vectors, said tester including means for combining said sequence of output vectors into a single characterizing test sum vector, the improvement comprising: means for adding the most significant output bit of said combining means to the least significant bits of said output vector sequence.
Claim 9
Independent Claim
166 words
An apparatus for fault testing logic circuits having pluralities of input and output points, said apparatus comprising: an oscillator providing a stream of clock pulses at a convenient rate, reseTtable means for counting said clock pulses up to a predetermined number, an accumulator for summing a sequence of binary vectors applied to its input points, means for applying the most significant output bit of said accumulator to the least significant carry input thereof, an interface matrix for applying the count from said counting means to the input points of said logic circuit and for applying the signals appearing at the output points of said logic circuit as input vectors to said accumulator, a source of a reference vector indicative of a properly operating logic circuit of the type under test, and means responsive to the attainment of the predetermined number in said counting means for indicating a lack of correspondence between the accumulator sum and said reference vector thereby denoting a fault in said logic circuit.
Claim 10
Independent Claim
166 words
An apparatus for fault testing logic circuits having pluralities of input and output points, said apparatus comprising: an oscillator providing a stream of clock pulses at a convenient rate, reseTtable means for counting said clock pulses up to a predetermined number, an accumulator for summing a sequence of binary vectors applied to its input points, means for applying the most significant output bit of said accumulator to the least significant carry input thereof, an interface matrix for applying the count from said counting means to the input points of said logic circuit and for applying the signals appearing at the output points of said logic circuit as input vectors to said accumulator, a source of a reference vector indicative of a properly operating logic circuit of the type under test, and means responsive to the attainment of the predetermined number in said counting means for indicating a lack of correspondence between the accumulator sum and said reference vector thereby denoting a fault in said logic circuit.
Claim 11
Dependent Claim
92 words
The apparatus of claim 6 further comprising a plurality of different matrices, each one useful with a different type of logic circuit and each one interchangeable with said interface matrix, each one of said plurality of matrices comprising: means for coupling a predetermined number of bits of the count from said counting means to the input points of said logic circuit, means for coupling the signals appearing at the output points of said logic circuit as input vectors to said accumulator, and means for coupling said reference vector to said indicating means.
Claim 12
Dependent Claim
66 words
The apparatus of claim 6 in which a testing interface matrix is substituted for said interface matrix to permit self-testing of the apparatus, said testing interface matrix comprising: means for coupling the count from said counting means directly to said accumulator as input vectors, and means for coupling to said indicating means a reference vector equal to the sum of the counts from saiad counting means.
Claim 13
Dependent Claim
87 words
In a logic circuit tester including an accumulator for adding a sequence of vectors, the method of self-testing said tester comprising the steps of: applying a sequence of test vectors to said accumulator to produce a single test sum vector, adding carries from the most significant bit of said single test sum vector to the sequence of test vectors at the least significant bit thereof, and checking for the correspondence of the single test sum vector with a predetermined reference sum vector characteristic of a fault-free tester.
Claim 14
Dependent Claim
87 words
In a logic circuit tester including an accumulator for adding a sequence of vectors, the method of self-testing said tester comprising the steps of: applying a sequence of test vectors to said accumulator to produce a single test sum vector, adding carries from the most significant bit of said single test sum vector to the sequence of test vectors at the least significant bit thereof, and checking for the correspondence of the single test sum vector with a predetermined reference sum vector characteristic of a fault-free tester.
Claim 15
Dependent Claim
105 words
The logic circuit tester of claim 1 in which said accumulator comprises a multidigit binary full adder including an overflow output bit and a least significant carry input bit, a multidigit storage register cooperating with said binary full adder to hold intermediate values of said test sum vector and means for coupling each digit of said storage register, other than the digit holding said overflow bit, to the corresponding input digit of said binary full adder; and said overflow bit adding means comprises a lead connecting the storage register digit holding said overflow bit to the least significant carry input of said binary full adder.
Claim 16
Dependent Claim
105 words
The logic circuit tester of claim 6 in which said accumulator comprises a multidigit binary full adder including an overflow output bit and a least significant carry input bit, a multidigit storage register cooperating with said binary full adder to hold intermediate values of said test sum vector and means for coupling each digit of said storage register, other than the digit holding said overflow bit, to the corresponding input digit of said binary full adder; and said overflow bit adding means comprises a lead connecting the storage register digit holding said overflow bit to the least significant carry input of said binary full adder.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-12 | 1978-11-11 | 1979-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-12 | 1982-11-11 | 1983-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-12 | 1986-11-11 | 1987-05-13 | $7700.00 | Window Closed / Lapsed |