Communications control apparatus for the use with a cache store

Claim 2

A processor communications control apparatus for controlling the retrieval of data information from either an addressable cache store in an electronic data processor or an addressable main memory store according to store address signals identifying the store location of the data information, said apparatus comprising: command means for generating timing signals in response to the store address signals; a base adder connected to said command means and to receive said store address signals for adding a base address portion to the store address signals in response to a first timing signal; checking means for checking the cache store for the data information according to the store address signals; comparator means connected to said checking means for generating a match signal in response to the determination that the data information is in the cache store; a port means connected to receive the added address signals from said base adder for providing a communication connection between the processor and the main memory store; an interrupt generator for generating an interrupt signal to the main memory store to provide communication access between the processor and the main memory store through said port means in response to a second timing signal from said command means and a signal from the port means that a communication connection is available; said match signal being generated before the occurrence of said second timing signal, said match signal controlling said interrupt generator to inhibit the generation of said interrupt signal.

Claim 3

A processor communications control apparatus as described in claim 1 wherein said command means generates a signal activating the addressing of the cache store in response to the match signal to transmit the addressed data information for utilization by the processor.

Claim 4

A processor communication control apparatus for controlling the retrieval of data information from either an addressable cache store in an electronic data processor or an addressable main memory store according to store address signals identifying the store location of the data information, saiD apparatus comprising: an address register for storing the store address signals of the data information to be retrieved; a command means connected to said address register for generating command timing signals in response to the store address signals; a base adder connected to said command means and to said address register for adding a base address portion to the store address signals in response to a first command timing signal; a plurality of connecting port means for providing a communication connection between the processor and the main memory store; a port select means connected to receive the added address signals from said base adder for selecting the one of the plurality of port means to be used for communication with the main memory store; an interrupt generator for generating an interrupt signal to the main memory store to provide communications access between the processor and the main memory store through the selected port means in response to a second timing signal from said command means; checking means connected to said address register for checking the cache store for the data information according to the store address signals; and comparator means connected to said checking means for generating a match signal in response to the determination that the data information is in the cache store; said match signal being generated before the occurrence of said second timing signal, said match signal controlling said interrupt generator to inhibit the generation of said interrupt signal and activating the cache store to transmit the addressed data information for utilization by the processor.

Claim 5

A processor communication control apparatus for controlling the retrieval of data information from either an addressable cache store in an electronic data processor or an addressable main memory store according to store address signals identifying the store location of the data information, saiD apparatus comprising: an address register for storing the store address signals of the data information to be retrieved; a command means connected to said address register for generating command timing signals in response to the store address signals; a base adder connected to said command means and to said address register for adding a base address portion to the store address signals in response to a first command timing signal; a plurality of connecting port means for providing a communication connection between the processor and the main memory store; a port select means connected to receive the added address signals from said base adder for selecting the one of the plurality of port means to be used for communication with the main memory store; an interrupt generator for generating an interrupt signal to the main memory store to provide communications access between the processor and the main memory store through the selected port means in response to a second timing signal from said command means; checking means connected to said address register for checking the cache store for the data information according to the store address signals; and comparator means connected to said checking means for generating a match signal in response to the determination that the data information is in the cache store; said match signal being generated before the occurrence of said second timing signal, said match signal controlling said interrupt generator to inhibit the generation of said interrupt signal and activating the cache store to transmit the addressed data information for utilization by the processor.

Claim 6

A process communications control apparatus for controlling the retrieval of data information from either an addressable cache store in an electronic data processor or an addressable main memory store including command means for generating timing signals in response to the store address signals, a base adder connected to said command means and to receive said store address signals for adding a base address portion to the store address signals in response to a first timing signal, a port means connected to receive the added address signals from said base adder for providing a communication connection between the processor and the main memory store, and an interrupt generator for generating an interrupt signal to the main memory store to provide communications access between the processor and the main memory store through said port means in response to a second timing signal from said command means and a signal from the port means that a communication connection is available, wherein the inprovement comprises: checking means for checking the cache store for the data information according to the store address signals; and comparator means connected to said checking means for generating a match signal in response to the determination that the data information is in the cache store; and means for coupling said checking means and said comparator means to said command means so that said operations are performed by said checking and said comparator means at the same time that the base adder and port means are performing their operations, said match signal being generated before the occurrence of said second timing signal, said match signal controlling said interrupt generator to inhibit the generation of said interrupt signal and controlling said command means to generate a third timing signal to activate the addressing of the cache store to transmit the addressed data information for utilization by the processor.

Claim 7

A process communications control apparatus for controlling the retrieval of data information from either an addressable cache store in an electronic data processor or an addressable main memory store including command means for generating timing signals in response to the store address signals, a base adder connected to said command means and to receive said store address signals for adding a base address portion to the store address signals in response to a first timing signal, a port means connected to receive the added address signals from said base adder for providing a communication connection between the processor and the main memory store, and an interrupt generator for generating an interrupt signal to the main memory store to provide communications access between the processor and the main memory store through said port means in response to a second timing signal from said command means and a signal from the port means that a communication connection is available, wherein the inprovement comprises: checking means for checking the cache store for the data information according to the store address signals; and comparator means connected to said checking means for generating a match signal in response to the determination that the data information is in the cache store; and means for coupling said checking means and said comparator means to said command means so that said operations are performed by said checking and said comparator means at the same time that the base adder and port means are performing their operations, said match signal being generated before the occurrence of said second timing signal, said match signal controlling said interrupt generator to inhibit the generation of said interrupt signal and controlling said command means to generate a third timing signal to activate the addressing of the cache store to transmit the addressed data information for utilization by the processor.

Claim 12

A method according to claim 6 further including the step of generating a portion of the cache address signals from the step of comparing, the generated cache address signal portion being used with a portion of the accepted address signals to accomplish the retrieval of data information from the cache store.