Abstract A binary data storage system of a data processing system is comprised of electrically independent storage modules, each module comprised of a matrix of electrically independent storage devices, with each storage device being an integral circuit element comprised of a first matrix of binary storage cells and associated selection circuitry, and a second matrix of binary storage cells and associated selection circuitry. The design of the binary storage cell of the first matrix and associated selection circuitry is such that a large number of storage cells can occupy a unit space but provide relatively slow access to the binary data manifested by the cell. The second matrix of binary storage cells and associated selection circuitry is formed in such a way that a relatively small number of storage cells are provided with a relatively high speed of access to the binary data manifested in the storage cells. Each storage device has a single terminal for the transfer of a single binary bit to or from the storage device. Each of the previously mentioned storage modules also has a single terminal for the transfer of a single binary bit to or from the storage module. All of the terminals of the storage devices are connected in common to the terminal of a storage module. One storage module is provided for each binary bit of a data processing system binary data word to be transferred between the storage system and the central processing unit of the data processing system. The most recently accessed binary data will be manifested in the high speed storage cells of the second matrix such that when address information is sent to the storage system, a large percentage of the requests for access to the storage system will find the data in the high speed portion of each of the storage devices providing an effective access time to the data in the storage system significantly faster than if the access to the data were required to be made to the storage cells of the first matrix.
An integral hierarchical storage device comprising: a circuit chip, a first array of a plurality of binary storage cells on said chip for the storage of binary data; a second array of a plurality of binary storage cells on said chip for the storage of binary data; means interconnecting said first and second arrays for the transfer of binary data therebetween; first selection signalling means connected to said first array, the combined operation of said first array of storage and said first selection means operative in a first predetermined duration to provide access to a plurality of binary storage cells in said first array for the transfer of data by said interconnecting means; second selection signalling means connected to said second array, the combined operation of said second array of storage and said second selection means operative in a second predetermined duration less than said first predetermined duration to provide access to a particular one of said binary storage cells in said second array for the transfer of data by said interconnecting means; and circuit chip input/output means, connected to all of said storage cells of said second array and operative in response to said second selection means, for transferring data to or from a particular one of said storage cells of said second array of storage.
Claim 2
Dependent Claim
217 words
An integral hierarchical storage device comprising: a circuit chip, a first array of a plurality of binary storage cells on said chip for the storage of binary data; a second array of a plurality of binary storage cells on said chip for the storage of binary data; means interconnecting said first and second arrays for the transfer of binary data therebetween; first selection signalling means connected to said first array, the combined operation of said first array of storage and said first selection means operative in a first predetermined duration to provide access to a plurality of binary storage cells in said first array for the transfer of data by said interconnecting means; second selection signalling means connected to said second array, the combined operation of said second array of storage and said second selection means operative in a second predetermined duration less than said first predetermined duration to provide access to a particular one of said binary storage cells in said second array for the transfer of data by said interconnecting means; and circuit chip input/output means, connected to all of said storage cells of said second array and operative in response to said second selection means, for transferring data to or from a particular one of said storage cells of said second array of storage.
Claim 3
Dependent Claim
204 words
A storage module comprising: an array of hierarchical storage devices, each comprised of slow access speed binary storage cells and high access speed binary storage cells, said high access speed storage cells manifesting the binary data contained in the most recently used slow access speed storage ceLls; cell selection means connected to all of said storage devices, including means for identifying and providing access to a particular one of said slow access speed binary storage cells of all said storage devices, and including means for providing access to binary data of said slow access speed storage cells in a particular one of said high access speed storage cells of all of said storage devices; data transfer means associated with each of said storage devices including terminal means and gating means for interconnecting said terminal and said particular one of said high access speed storage devices; a module terminal connected to all of said storage device terminal means; and device selection means connected to all of said data transfer gating means for selecting a particular one of said storage devices, whereby said module terminal is interconnected with said particular one of said high access speed storage cells of said particular one of said storage devices.
Claim 4
Dependent Claim
204 words
A storage module comprising: an array of hierarchical storage devices, each comprised of slow access speed binary storage cells and high access speed binary storage cells, said high access speed storage cells manifesting the binary data contained in the most recently used slow access speed storage ceLls; cell selection means connected to all of said storage devices, including means for identifying and providing access to a particular one of said slow access speed binary storage cells of all said storage devices, and including means for providing access to binary data of said slow access speed storage cells in a particular one of said high access speed storage cells of all of said storage devices; data transfer means associated with each of said storage devices including terminal means and gating means for interconnecting said terminal and said particular one of said high access speed storage devices; a module terminal connected to all of said storage device terminal means; and device selection means connected to all of said data transfer gating means for selecting a particular one of said storage devices, whereby said module terminal is interconnected with said particular one of said high access speed storage cells of said particular one of said storage devices.