Compound and multilevel memories

Claim 2

In an information processing system, a compound memory comprising a random access memory array comprising storage locations for the storage of blocks of words, and an associative memory array comprising storage locations for the storage of a plurality of words with each of said plurality of word storage locations being directly connected to a corresponding storage location defining a block of words in said random access array whereby access to the random access array is achieved using the associate array without the necessity for an intervening addressing element.

Claim 3

A memory hierarchy comprising at least two levels of memories, at least one of said two levels of memories including a compound memory comprising a random access memory array comprising storage locations for the storage of blocks of words, and an associative memory array comprising storage locations for the storage of a plurality of words with each of said plurality of word storage locations being directly connected to a corresponding storage location defining a block of words in said random access array whereby access to the random access array is achieved using the associate array without the necessity for an intervening addressing element; and addressing means connected to said two levels of memories for addressing the other level of said two levels of memories when an addressed block of words is not accessed from said one level of memory.

Claim 4

A memory hierarchy comprising at least two levels of memories, at least one of said two levels of memories including a compound memory comprising a random access memory array comprising storage locations for the storage of blocks of words, and an associative memory array comprising storage locations for the storage of a plurality of words with each of said plurality of word storage locations being directly connected to a corresponding storage location defining a block of words in said random access array whereby access to the random access array is achieved using the associate array without the necessity for an intervening addressing element; and addressing means connected to said two levels of memories for addressing the other level of said two levels of memories when an addressed block of words is not accessed from said one level of memory.

Claim 5

An information processing system including a control section having control memories providing control words and a data section having a data memory providing data words connected to said control section and controlled by said control words, said control section comprises, a first control memory comprising storage locations having stored therein a number of blocks of control words; a backup control memory comprising an additional number of storage locations having stored therein blocks of control words; addressing means for directly providing the same addresses to said first control memory and said backup control memory independently of said data section when an addressed block of words is not contained in said first control memory; and means for transferring blocks of control words from said backup control memory to said first control memory.

Claim 6

An information processing system including a control section having control memories providing control words and a data section having a data memory providing data words connected to said control section and controlled by said control words, said control section comprises, a first control memory comprising storage locations having stored therein a number of blocks of control words; a backup control memory comprising an additional number of storage locations having stored therein blocks of control words; addressing means for directly providing the same addresses to said first control memory and said backup control memory independently of said data section when an addressed block of words is not contained in said first control memory; and means for transferring blocks of control words from said backup control memory to said first control memory.

Claim 7

A multilevel memory hierarchy comprising, first, second, and third memories, each of said memories having common addresses for accessing corresponding blocks of words and each said memory operating at a different speed; addressing means connected to each said memory for addressing said blocks of words in parallel; first transfer means for transferring addressed information blocks of words of a first size between said first and second memories; and second transfer means for transferring addressed information blocks of words of a second size between said second and third memories, whereby a block of words desired from said first memory is transferred to said first memory from either the second or third memory when such desired block of words is not contained in said first memory.

Claim 8

A multilevel memory hierarchy comprising, first, second, and third memories, each of said memories having common addresses for accessing corresponding blocks of words and each said memory operating at a different speed; addressing means connected to each said memory for addressing said blocks of words in parallel; first transfer means for transferring addressed information blocks of words of a first size between said first and second memories; and second transfer means for transferring addressed information blocks of words of a second size between said second and third memories, whereby a block of words desired from said first memory is transferred to said first memory from either the second or third memory when such desired block of words is not contained in said first memory.

Claim 11

A compound memory comprising a random memory access array comprising a plurality of storage locations for the storage of blocks of words and including a plurality of accessing means, one for each block of words; asSociative memory array means including a plurality of storage locations for the storage of associative words wherein one associative word is provided for each one of said plurality of blocks of words and including a plurality of match identifier elements wherein there is one match identifier element for each associative word, one of said match identifier elements being energized when the bits of an input address are identical to the bits of its corresponding associative word; and means directly connecting each of said match identifier elements to a corresponding one of said accessing means to permit an energized one of said match identifier elements to directly access the corresponding block of words.

Claim 12

A compound memory comprising a random memory access array comprising a plurality of storage locations for the storage of blocks of words and including a plurality of accessing means, one for each block of words; asSociative memory array means including a plurality of storage locations for the storage of associative words wherein one associative word is provided for each one of said plurality of blocks of words and including a plurality of match identifier elements wherein there is one match identifier element for each associative word, one of said match identifier elements being energized when the bits of an input address are identical to the bits of its corresponding associative word; and means directly connecting each of said match identifier elements to a corresponding one of said accessing means to permit an energized one of said match identifier elements to directly access the corresponding block of words.

Claim 13

An information processing system comprising a main memory having physical memory storage locations providing words of data; means for generating addresses comprising a number of bits, said addresses defining data contained in said main memory; means for changing the addresses generated by said address generating means into different addresses representing physical memory storage locations of said main memory, said address changing means comprising a compound memory; said compound memory comprising a random access memory array comprising storage locations for the storage of blocks of words, and an associative memory array comprising storage locations for the storage of a plurality of words with each of said plurality of word storage locations being directly connected to a corresponding storage location defining a block of words in said random access array whereby access to the random access array is achieved using the associate array without the necessity for an intervening addressing element.

Claim 14

An information processing system comprising a main memory having physical memory storage locations providing words of data; means for generating addresses comprising a number of bits, said addresses defining data contained in said main memory; means for changing the addresses generated by said address generating means into different addresses representing physical memory storage locations of said main memory, said address changing means comprising a compound memory; said compound memory comprising a random access memory array comprising storage locations for the storage of blocks of words, and an associative memory array comprising storage locations for the storage of a plurality of words with each of said plurality of word storage locations being directly connected to a corresponding storage location defining a block of words in said random access array whereby access to the random access array is achieved using the associate array without the necessity for an intervening addressing element.

Claim 17

A data processing system comprising a main memory comprising a random access memory array comprising storage locations for the storage of blocks of words, and an associative memory array comprising storage locations for the storage of a plurality of words with each of said plurality of word storage locations being directly connected to a corresponding storage location defining a block of words in said random access array whereby access to the random access array is achieved using the associate array without the necessity for an intervening addressing element; means for generating addresses for accessing blocks of words in said main memory; and data utilization means for utilizing the data contained in said main memory.

Claim 18

A data processing system comprising a main memory comprising a random access memory array comprising storage locations for the storage of blocks of words, and an associative memory array comprising storage locations for the storage of a plurality of words with each of said plurality of word storage locations being directly connected to a corresponding storage location defining a block of words in said random access array whereby access to the random access array is achieved using the associate array without the necessity for an intervening addressing element; means for generating addresses for accessing blocks of words in said main memory; and data utilization means for utilizing the data contained in said main memory.