Selectively controllable shift register and counter divider network

Claim 2

A divider network for dividing sequentially occurring input signals comprising: a. a counter including one through N binary cells, each capable of achieving first and second states and generating binary output signals representative of said states, said counter responsive to said input signals to effect the counting thereof and said one of said binary cells further being responsive to applied control signals for controlling the states of said one binary cell, the state of said one binary cell being sequentially transferred through the other binary cells of said counter to continuously control the count therein during a divide sequence; b. select means for generating at least one output enable signal representative of a number by which said input signals are to be divided; c. decode means responsive to the binary output signals from said binary cells and to the at least one output enable signal from said select means for providing the control signals to said one binary cell, said control signals changing during the divide sequence to alter the state of said one binary cell in accordance with the number specified by the at least one output enable signal when said counter achieves a specified count associated with an individual one of said at least one output enable signal; and d. output means responsive to the binary output signals from said binary cells for generating an output signal representative of a number of said input signals applied to said counter divided by the number represented by the at least one output enable signal from said select means when the Nth binary cell is in its first state and the remaining binary cells are each in their second state.

Claim 3

a divider network for selectively dividing sequentially occurring input signals comprising: a. a counter including one through N binary cells, each capable of achieving first and second states and generating binary output signals representative of said states, said counter responsive to said input signals and to applied control signals, said control signals controlling the states of said binary cells at the time of occurrence of said input signals; b. decode means responsive to the binary output signals from said binary cells and to a plurality of enable signals for providing the control signals to said counter, said enable signals collectively representing a number by which said input signals are to be divided, and each of said plurality of enable signals effecting a respective recognizable change in said control signals when said counter achieves a specified count associated with a corresponding one of said enable signals; c. first output means responsive to the binary output signals from said binary cells for generating a first output signal representative of a number of said input signals applied to said counter divided by the number represented by said plurality of enable signals when the Nth binary cell is in its first state and the remaining binary cells are each in their second state; d. select means including a control element capable of achieving first and second states and generating first and second logic signals representative of the states of said control element in response to said first output signal from said first output means, said select means further including select logic for providing, in a first instance, a first one of the enable signals to said decode means in response to the first logic signal from said control element when said control element is in its first state and providing, in a second instance, a second one of the enable signals to said decode means in response to the second logic signal from said control element when said control element is in its second state; and e. second output means responsive to the binary output signals from said binary cells and to the first logic signal from said control element for generating a second output signal representative of a number of said input signals applied to said counter divided by the number represented by the first and second enable signals when the Nth binary cell is in its first state, the remaining binary cells are in their second state and when said control element achieves its first state.

Claim 4

a divider network for selectively dividing sequentially occurring input signals comprising: a. a counter including one through N binary cells, each capable of achieving first and second states and generating binary output signals representative of said states, said counter responsive to said input signals and to applied control signals, said control signals controlling the states of said binary cells at the time of occurrence of said input signals; b. decode means responsive to the binary output signals from said binary cells and to a plurality of enable signals for providing the control signals to said counter, said enable signals collectively representing a number by which said input signals are to be divided, and each of said plurality of enable signals effecting a respective recognizable change in said control signals when said counter achieves a specified count associated with a corresponding one of said enable signals; c. first output means responsive to the binary output signals from said binary cells for generating a first output signal representative of a number of said input signals applied to said counter divided by the number represented by said plurality of enable signals when the Nth binary cell is in its first state and the remaining binary cells are each in their second state; d. select means including a control element capable of achieving first and second states and generating first and second logic signals representative of the states of said control element in response to said first output signal from said first output means, said select means further including select logic for providing, in a first instance, a first one of the enable signals to said decode means in response to the first logic signal from said control element when said control element is in its first state and providing, in a second instance, a second one of the enable signals to said decode means in response to the second logic signal from said control element when said control element is in its second state; and e. second output means responsive to the binary output signals from said binary cells and to the first logic signal from said control element for generating a second output signal representative of a number of said input signals applied to said counter divided by the number represented by the first and second enable signals when the Nth binary cell is in its first state, the remaining binary cells are in their second state and when said control element achieves its first state.

Claim 5

A divider network for dividing sequentially occurring input signals comprising: a. first and second counters, each including N binary cells capable of achieving first and second states and generating binary output signals representative of said states, said first counter responsive to first sequentially occurring input signals and said second counter responsive to second sequentially applied input signals, said first and second counters responsive to first and second control signals respectively for controlling the states of said binary cells at the time of occurrence of the first and second input signals applied to said first and second counters respectively; b. first and second decode means associated with said first and second counters respectively, each of said decode means including means responsive to the binary output signals from the binary cells of their respective counters and each responsive to enable signals for providing the control signals to their respective counters, said enable signals collectively representing a number by which the first input signals applied to said first counter are to be divided and each of said enable signals effecting a respective recognizable change in said control signals when each of said counters achieves a specified count associated with a corresponding one of said enable signals, said first decode means further including first output means responsive to the binary output signals from the binary cells of said first counter for applying said second input signals to said second counter as a signal representative of a number of the first input signals applied to said first counter divided by a number represented by the enable signals of said first decode means when the Nth binary cell of said first counter is in its first state and the remaining binary cells are each in their second state; c. first and second select means associated with said first and second decode means respectively, said second select means including a control element capable of achieving first and second states and generating first and second logic signals respectively representative of the states of said control element in response to the second input signal from said first output means, each of said select means including select logic for providing, in a first instance, a first one of the enable signals to their respective decode means in response to the first logic signal from said control element and providing, in a second instance, a second one of the enable signals to their respective decode means in response to the second logic signal from said control element, said second decode means further including second output means responsive to the binary output signals from the binary cells of said second counter and to the first logic signal from said control element for generating a final output signal representative of a number of the first input signals applied to said first counter divided by the sum of the numbers represented by the enable signals.

Claim 6

A divider network for dividing sequentially occurring input signals comprising: a. first and second counters, each including N binary cells capable of achieving first and second states and generating binary output signals representative of said states, said first counter responsive to first sequentially occurring input signals and said second counter responsive to second sequentially applied input signals, said first and second counters responsive to first and second control signals respectively for controlling the states of said binary cells at the time of occurrence of the first and second input signals applied to said first and second counters respectively; b. first and second decode means associated with said first and second counters respectively, each of said decode means including means responsive to the binary output signals from the binary cells of their respective counters and each responsive to enable signals for providing the control signals to their respective counters, said enable signals collectively representing a number by which the first input signals applied to said first counter are to be divided and each of said enable signals effecting a respective recognizable change in said control signals when each of said counters achieves a specified count associated with a corresponding one of said enable signals, said first decode means further including first output means responsive to the binary output signals from the binary cells of said first counter for applying said second input signals to said second counter as a signal representative of a number of the first input signals applied to said first counter divided by a number represented by the enable signals of said first decode means when the Nth binary cell of said first counter is in its first state and the remaining binary cells are each in their second state; c. first and second select means associated with said first and second decode means respectively, said second select means including a control element capable of achieving first and second states and generating first and second logic signals respectively representative of the states of said control element in response to the second input signal from said first output means, each of said select means including select logic for providing, in a first instance, a first one of the enable signals to their respective decode means in response to the first logic signal from said control element and providing, in a second instance, a second one of the enable signals to their respective decode means in response to the second logic signal from said control element, said second decode means further including second output means responsive to the binary output signals from the binary cells of said second counter and to the first logic signal from said control element for generating a final output signal representative of a number of the first input signals applied to said first counter divided by the sum of the numbers represented by the enable signals.

Claim 7

A divider network for dividing sequentially occurring input signals comprising: a. a shift register counter including one through N flip-flOps, each capable of achieving first and second states and generating binary output signals representative of said states, each of said flip-flops receiving said input signals for simultaneously operating said flip-flops, said one of said flip-flops further receiving applied control signals, said control signals controlling the states of said one of said flip-flops at the time of occurrence of said input signals; b. select means for selectively generating output enable signals representative of a number by which said input signals are to be divided; c. a plurality of AND gates, each receiving a binary output signal from specified ones of said flip-flops, and specified ones of said AND gates each receiving a one of the output enable signals from said select means, the specified ones of said plurality of AND gates each generating a logic term signal in response to a received output enable signal when the binary output signals received thereby represent a prescribed count in said counter; d. an OR gate responsive to the logic term signal generated by each of said plurality of AND gates for providing the control signals to said one of said flip-flops in accordance with a recognizable change effected by each logic term signal; and e. an output AND gate responsive to the binary output signals from said flip-flops for generating an output signal representative of a number of the input signals applied to said counter divided by a number represented by the output enable signals of said select means when the Nth flip-flop is in its first state and the remaining flip-flops are each in their second state.

Claim 8

A divider network for dividing sequentially occurring input signals comprising: a. a shift register counter including one through N flip-flOps, each capable of achieving first and second states and generating binary output signals representative of said states, each of said flip-flops receiving said input signals for simultaneously operating said flip-flops, said one of said flip-flops further receiving applied control signals, said control signals controlling the states of said one of said flip-flops at the time of occurrence of said input signals; b. select means for selectively generating output enable signals representative of a number by which said input signals are to be divided; c. a plurality of AND gates, each receiving a binary output signal from specified ones of said flip-flops, and specified ones of said AND gates each receiving a one of the output enable signals from said select means, the specified ones of said plurality of AND gates each generating a logic term signal in response to a received output enable signal when the binary output signals received thereby represent a prescribed count in said counter; d. an OR gate responsive to the logic term signal generated by each of said plurality of AND gates for providing the control signals to said one of said flip-flops in accordance with a recognizable change effected by each logic term signal; and e. an output AND gate responsive to the binary output signals from said flip-flops for generating an output signal representative of a number of the input signals applied to said counter divided by a number represented by the output enable signals of said select means when the Nth flip-flop is in its first state and the remaining flip-flops are each in their second state.

Claim 9

A divider network for dividing sequentially occurring input signals comprising: a. a counter including one through N flip-flops, each capable of achieving set and reset states and generating binary output signals representative of said states, each of said flip-flops responsive to a reset signal for resetting said counter, each of said flip-flops receiving said input signals for simultaneously operating said flip-flops, and said one of said flip-flops further receiving applied control signals for controlling the states of said one of said flip-flops at the time of occurrence of said input signals; b. a plurality of OR gates, each having input terminals for receiving logic signals collectively representative of a number by which the input signals are to be divided and each generating an output enable signal in response to logic signals selectively applied thereto; c. switch means for selectively connecting the logic signals to the input terminals of said plurality of OR gates; d. a control flip-flop capable of achieving set and reset states and responsive to said reset signal for placing said control flip-flop in a reset state, said control flip-flop further responsive to a first output signal and being connected to said switch means for providing said logic signals thereto in accordance with the states of said control flip-flop; e. means responsive to the binary output signals from said one through N flip-flops and to the output enable signal from each of said plurality of OR gates for providing the control signals to said one of said flip-flops, each output enable signal effecting a respective recognizable change in the control signals when said counter achieves a specified count associated with a corresponding one of said output enable signals; f. first output means responsive to the binary output signals from said flip-flops of said counter for providing said first output signal to said control flip-flop when the Nth flip-flop is in its set state and the remaining flip-flops are each in their reset state; and g. second output means responsive to the first output signal and to one of the logic signals from said control flip-flop for generating a second output signal representative of a number of the input signals applied to said counter divided by the number represented by the logic signals applied to said plurlaity of OR gates from said control flip-flop.

Claim 10

A divider network for dividing sequentially occurring input signals comprising: a. a counter including one through N flip-flops, each capable of achieving set and reset states and generating binary output signals representative of said states, each of said flip-flops responsive to a reset signal for resetting said counter, each of said flip-flops receiving said input signals for simultaneously operating said flip-flops, and said one of said flip-flops further receiving applied control signals for controlling the states of said one of said flip-flops at the time of occurrence of said input signals; b. a plurality of OR gates, each having input terminals for receiving logic signals collectively representative of a number by which the input signals are to be divided and each generating an output enable signal in response to logic signals selectively applied thereto; c. switch means for selectively connecting the logic signals to the input terminals of said plurality of OR gates; d. a control flip-flop capable of achieving set and reset states and responsive to said reset signal for placing said control flip-flop in a reset state, said control flip-flop further responsive to a first output signal and being connected to said switch means for providing said logic signals thereto in accordance with the states of said control flip-flop; e. means responsive to the binary output signals from said one through N flip-flops and to the output enable signal from each of said plurality of OR gates for providing the control signals to said one of said flip-flops, each output enable signal effecting a respective recognizable change in the control signals when said counter achieves a specified count associated with a corresponding one of said output enable signals; f. first output means responsive to the binary output signals from said flip-flops of said counter for providing said first output signal to said control flip-flop when the Nth flip-flop is in its set state and the remaining flip-flops are each in their reset state; and g. second output means responsive to the first output signal and to one of the logic signals from said control flip-flop for generating a second output signal representative of a number of the input signals applied to said counter divided by the number represented by the logic signals applied to said plurlaity of OR gates from said control flip-flop.

Claim 11

In a divider network of the type having a shift register counter comprised of one through N binary cells, each capable of achieving first and second states and generating binary output signals representative of said states, a method of dividing input signals sequentially applied to said counter, comprising the steps of: a. generating at least one divide signal representative of a number by which said input signals are to be divided; b. continuously applying control signals to said one binary cell for controlling the states thereof, the state of said one binary cell being sequentially transferred through the other binary cells of said counter to continuously control the count therein during a divide sequence as each input signal is applied to said counter, said control signals exhibiting a recognizable change therein during the divide sequence in accordance with the number specified by the at least one divide signal when said counter achieves a prescribed count associated with an individual one of said at least one divide signal; and c. generating an output signal representative of a number of the input signals divided by the number specified by the divide signal when the Nth binary cell is in its first state and the remaining binary cells are each in their second state.

Claim 12

In a divider network of the type having a shift register counter comprised of one through N binary cells, each capable of achieving first and second states and generating binary output signals representative of said states, a method of dividing input signals sequentially applied to said counter, comprising the steps of: a. generating at least one divide signal representative of a number by which said input signals are to be divided; b. continuously applying control signals to said one binary cell for controlling the states thereof, the state of said one binary cell being sequentially transferred through the other binary cells of said counter to continuously control the count therein during a divide sequence as each input signal is applied to said counter, said control signals exhibiting a recognizable change therein during the divide sequence in accordance with the number specified by the at least one divide signal when said counter achieves a prescribed count associated with an individual one of said at least one divide signal; and c. generating an output signal representative of a number of the input signals divided by the number specified by the divide signal when the Nth binary cell is in its first state and the remaining binary cells are each in their second state.