Pulse counter having selectable whole and fractional number division

Claim 2

A pulse train modification system comprising: a. A pulse transmission path including a blocking circuit means positioned therein having a normal input means and an inhibit input means, said blocking circuit means being operative to receive said pulse train at said normal input means and prevent passage of a pulse whenever a pulse has been applied to said inhibit input means: b. Divider circuit means positioned in said pulse transmission path to receive pulses passed by said blocking circuit means and produce a divider output pulse in response to a preselected whole number of received pulses; c. Feedback means connected between the output means of said divider circuit means and the inhibit input means of said blocking circuit means and being operative to cause pulses to be applied to said inhibit input means to effect the blocking of pulses from said pulse train in a manner directly related to the arrangement of bits of the binary equivalent of the error between the divider output and a desired relationship of the pulses of said train; and d. Output means coupled with the output of said divider circuit means for extracting an output having the desired relationship.

Claim 5

The system recited in claim 2 wherein said divider circuit means comprises a counter having a plurality of pulse output-type bistable stages and means operatively associated therewith for summing the outputs of selected stages to produce the desired whole number division.

Claim 6

The system recited in claim 3 wherein said means for summing the outputs of selected bistable stages comprises a pluraLity of switch means one associated with the output of each of said bistable stages.

Claim 7

The system recited in claim 2 wherein said feedback means comprises a binary correction counter means including a plurality of pulse output-type bistable stages and means operatively associated therewith for summing the outputs of selected stages to produce outputs from said binary correction counter which are directly related to the binary equivalent of the fractional portion of said factor.

Claim 8

The system recited in claim 5 wherein said means for summing the outputs of selected bistable stages comprises a plurality of switch means one associated with the output of each of said bistable stages.

Claim 9

The system recited in claim 6 wherein said switch means are responsive to signals indicative of a change in the pulse signals from said repetitive source to cause a change in said selection corresponding to any required change in the binary equivalent of the fractional portion of said factor:

Claim 10

The system recited in claim 7 wherein said divider circuit means comprises a counter having a plurality of pulse output-type bistable stages and means operatively associated therewith for summing the outputs of selected stages to produce the desired whole number division, said means for summing the outputs of selected stages comprising a plurality of switch means one associated with the output of each of said bistable stages and each switch means responsive to signals indicative of a change in the data pulse signals from said repetitive source to cause a change in said selection corresponding to any required change in the whole number division.

Claim 13

A digital measuring system comprising: a. A digital sensor means operatively associated with a desired parameter to be measured and being operative to produce n pulses for each reference unit of said parameter to be measured and wherein n comprises a whole number portion and a fractional portion; b. A blocking circuit means having a normal input means and an inhibit input means, said blocking circuit means being operative to pass pulses applied to said normal input means unless a pulse is also applied to said inhibit input means; c. Means applying the pulses from said digital sensor means to the normal input means of said blocking circuit means; d. Divider circuit means having its input means connected with the output means of said blocking circuit means and operative to receive pulses passed by said blocking circuit means and provide an output in response to a number of received pulses equal to the whole number portion of n; e. Feedback circuit means connected between the output of said divider circuit means and the inhibit input means of said blocking circuit means, said feedback circuit means including a binary correction counter means connected to receive pulses from the output of said divider circuit means and being operative to produce pulses directly related to the arrangement of bits of the binary equivalent of the fractional portion of n; f, Means applying the pulses produced by said binary correction counter means to said inhibit input means of said blocking circuit means to effect the blocking of pulsEs from said digital sensor means in a manner directly related to said pulses applied to said inhibit input means; and g. Utilization means coupled with the output of said divider circuit means.

Claim 14

A digital measuring system comprising: a. A digital sensor means operatively associated with a desired parameter to be measured and being operative to produce n pulses for each reference unit of said parameter to be measured and wherein n comprises a whole number portion and a fractional portion; b. A blocking circuit means having a normal input means and an inhibit input means, said blocking circuit means being operative to pass pulses applied to said normal input means unless a pulse is also applied to said inhibit input means; c. Means applying the pulses from said digital sensor means to the normal input means of said blocking circuit means; d. Divider circuit means having its input means connected with the output means of said blocking circuit means and operative to receive pulses passed by said blocking circuit means and provide an output in response to a number of received pulses equal to the whole number portion of n; e. Feedback circuit means connected between the output of said divider circuit means and the inhibit input means of said blocking circuit means, said feedback circuit means including a binary correction counter means connected to receive pulses from the output of said divider circuit means and being operative to produce pulses directly related to the arrangement of bits of the binary equivalent of the fractional portion of n; f, Means applying the pulses produced by said binary correction counter means to said inhibit input means of said blocking circuit means to effect the blocking of pulsEs from said digital sensor means in a manner directly related to said pulses applied to said inhibit input means; and g. Utilization means coupled with the output of said divider circuit means.

Claim 15

The measuring system recited in claim 10 wherein said digital sensor means is operatively associated with a flowmeter.

Claim 16

THe measuring system recited in claim 10 wherein said binary correction counter means includes gating circuit means operatively associated therewith and which gating means are responsive to signals indicative of a change in the fractional portion of n and are operative to effect a change in the output of said binary correction counter means corresponding to the binary equivalent of changes in the fractional portion of n.

Claim 17

The measuring system recited in claim 10 wherein said divider circuit means and said binary correction counter means each include gating circuit means which are responsive to signals indicative of a change in n and are operative to effect changes in the output of said divider circuit means and the binary correction counter means so that said divider circuit produces an output corresponding to the changed whole number portion of N n said binary correction counter means produces an output corresponding to the arrangement of bits of the binary equivalent of the fractional portion of n.