US3733471A
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US
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Recirculating counter
Assignee: NCR Voyix Corp
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Filing: 1971-12-07
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Granted: 1973-05-15
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Expires: 1991-12-07
Abstract
Abstract A four phase MOS-LSI dynamic recirculating binary counter which operates in an N bit time cycle and which counts in excess of 2N 1 counts is disclosed. The counter includes an N stage shift register counter and output logic. The output logic includes a latch which is set once each time cycle during a given bit time and reset by the first logic 0 signal from the shift register counter. If during the given bit time of the next cycle the latch is still set and the least significant shift register stage signal is logic 1, a signal is provided to set additional latch circuits which act as additional stages of the binary counter.
Inventors
- 👤 R Gilberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:33
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K23/00; H03K23/40; H03K23/42; H03K23/44; H03K23/64; H03K23/66
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
241 words
A cyclically operating N+1 stage counter capable of changing its count during any given cycle of operation, each cycle of operation being divided into N bit times, said counter comprising: an N stage shift register means operating in a continual shift manner so that whenever any signal representating one or another binary number is applied to the first stage thereof, a corresponding signal representating the same binary number is successively provided from each stage thereof during the next N successive bit times, said shift register registering a count during a given bit time of each cycle by each stage thereof providing a signal representing one or another of said binary numbers during said given bit time; coupling means, including logic means, for coupling the output of said Nth stage to the input of said first stage, said logic means, on command, modifying the signal provided by said Nth stage so that the count registered by said shift register during said given bit time of the next occurring cycle is different from the count registered during said given bit time of the then occurring cycle; decoding means responsive to the signal provided by said Nth stage for providing a signal whenever the Nth stage signal indicates the count registered by said shift register during the then occurring cycle is a certain count; and bistable means responsive to said decoding means signal for being set upon the occurrence of said decoding means signal.
Claim 2
Dependent Claim
241 words
A cyclically operating N+1 stage counter capable of changing its count during any given cycle of operation, each cycle of operation being divided into N bit times, said counter comprising: an N stage shift register means operating in a continual shift manner so that whenever any signal representating one or another binary number is applied to the first stage thereof, a corresponding signal representating the same binary number is successively provided from each stage thereof during the next N successive bit times, said shift register registering a count during a given bit time of each cycle by each stage thereof providing a signal representing one or another of said binary numbers during said given bit time; coupling means, including logic means, for coupling the output of said Nth stage to the input of said first stage, said logic means, on command, modifying the signal provided by said Nth stage so that the count registered by said shift register during said given bit time of the next occurring cycle is different from the count registered during said given bit time of the then occurring cycle; decoding means responsive to the signal provided by said Nth stage for providing a signal whenever the Nth stage signal indicates the count registered by said shift register during the then occurring cycle is a certain count; and bistable means responsive to said decoding means signal for being set upon the occurrence of said decoding means signal.
Claim 3
Dependent Claim
13 words
The invention according to claim 1 wherein said certain count is (2N- 1)
Claim 4
Dependent Claim
40 words
The invention according to claim 2 wherein said decoding means includes latching means for becoming set at said given time of each cycle of operation and for being reset by the first Nth stage signal representing said another binary number.
Claim 5
Dependent Claim
38 words
The invention according to claim 3 wherein said decoding means signal is provided during said given time so long as said latching means included in said decoding means remains set one bit time prior to said given time.
Claim 6
Dependent Claim
339 words
A cyclically operating N+1 stage counter capable of changing its count during any given cycle of operation, each cycle of operation being divided into N bit times, said counter comprising: an N stage shift register means operating in a continual shift manner so that whenever any signal representing one or another binary number is applied to the first stage thereof, a corresponding signal representing the same binary number is successively provided from each stage thereof during the next N successive bit times, said shift register registering a count during a given bit time of each cycle by each stage thereof providing a signal representing one or another of said binary numbers during said given bit time; coupling means, including logic means, for coupling the output of the Nth stage to the input of said first stage, said logic means, on command, modifying the signal provided by said Nth stage so that the count registered by said shift register during said given bit time of the next occurring cycle is different from the count registered during said given bit time of the then occurring cycle; decoding means responsive to the signal provided by said Nth stage for providing a signal whenever the Nth stage signal indicates the count registered by said shift register means during the then occurring cycle is a certain count; and bistable means responsive to said decoding means signal for being set upon the occurrence of said decoding means signal; wherein said certain count is (2N- 1); wherein said decoding means includes means for becoming set at said given time of each cycle of operation and for being reset by the first Nth stage signal representing said another binary number; wherein said decoding means signal is provided during said given time so long as said means included in said decoding means remains set one bit time prior to said time; and wherein each of said shift register means, logic means, and decoding means includes metal oxide semiconductor transistors connected to operate in a four-phase circuit configuration manner.
Claim 7
Dependent Claim
339 words
A cyclically operating N+1 stage counter capable of changing its count during any given cycle of operation, each cycle of operation being divided into N bit times, said counter comprising: an N stage shift register means operating in a continual shift manner so that whenever any signal representing one or another binary number is applied to the first stage thereof, a corresponding signal representing the same binary number is successively provided from each stage thereof during the next N successive bit times, said shift register registering a count during a given bit time of each cycle by each stage thereof providing a signal representing one or another of said binary numbers during said given bit time; coupling means, including logic means, for coupling the output of the Nth stage to the input of said first stage, said logic means, on command, modifying the signal provided by said Nth stage so that the count registered by said shift register during said given bit time of the next occurring cycle is different from the count registered during said given bit time of the then occurring cycle; decoding means responsive to the signal provided by said Nth stage for providing a signal whenever the Nth stage signal indicates the count registered by said shift register means during the then occurring cycle is a certain count; and bistable means responsive to said decoding means signal for being set upon the occurrence of said decoding means signal; wherein said certain count is (2N- 1); wherein said decoding means includes means for becoming set at said given time of each cycle of operation and for being reset by the first Nth stage signal representing said another binary number; wherein said decoding means signal is provided during said given time so long as said means included in said decoding means remains set one bit time prior to said time; and wherein each of said shift register means, logic means, and decoding means includes metal oxide semiconductor transistors connected to operate in a four-phase circuit configuration manner.
Claim 8
Dependent Claim
49 words
The invention according to claim 5 wherein said decoding means signal is provided during said given time so long as said means included in said decoding means is set one bit time prior to said given time and the then occurring Nth stage signal represents said one binary number.
Claim 9
Dependent Claim
20 words
The invention according to claim 6 wherein said one binary number is one and said another binary number is zero.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-05-14 | 1976-11-13 | 1977-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-05-14 | 1980-11-13 | 1981-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-05-14 | 1984-11-13 | 1985-05-15 | $7700.00 | Window Closed / Lapsed |