US3858304A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for fabricating small geometry semiconductor devices
Assignee: Raytheon Co
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Filing: 1974-01-30
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Granted: 1975-01-07
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Expires: 1994-01-30
Abstract
Abstract A process for fabricating small geometry semiconductor devices wherein an active region or regions are formed in a semiconductive layer and metalization patterns are formed on the surface thereof, while a resist pattern used to define the geometry of these regions and patterns is left temporarily in place between metal and semiconductor. Then, the resist is lifted off the surface of the oxide located between the metal and the semiconductive layer and whose geometry it controlled carrying with it the metalization lying on the resist surface and leaving very narrow strips of metalization in contact with the active regions.
Inventors
- 👤 Hayden M Leedy
- 👤 Jr Loren G Mccray
- 👤 Harry L Stover
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 08:54
CPC Classifications
H; H10; H10P; H10P95/00; H10P76/00; H10P76/20; H10W; H10W20/00; H10W20/40; Y; Y10; Y10S; Y10S148/00; Y10S148/106; Y10S148/139
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
204 words
A method of making semiconductor devices including the steps of: a. forming an insulating coating on the surface of a layer of semiconductive material; b. forming a resist pattern on said insulating coating; c. removing selected regions of said insulating coating which are exposed by openings in said resist pattern, thereby exposing an area or areas of said semiconductive layer; d. accelerating dopant ions into said exposed area or areas of said semiconductive layer and into the crystal lattice of said semiconductive layer to alter the conductivity thereof and to form planar P-N junctions in said semiconductive layer wherein said junctions terminate at said surface under said insulating coating; e. depositing metalization on the exposed surface area of said resist pattern and into contact with the exposed area or areas of said semiconductive layer to thereby make electrical contact to said P-N junctions, and thereafter f. removing said resist pattern from said insulating coating to thereby simultaneously remove the portion of said metalizatioN layer overlying said resist pattern, leaving intact the metalization in electrical contact with said semiconductive layer, whereby the ion implantation temperatures utilized during the acceleration of dopant ions into the semiconductor crystal lattice are insulfficient to deleteriously affect said resist pattern.
Claim 2
Independent Claim
204 words
A method of making semiconductor devices including the steps of: a. forming an insulating coating on the surface of a layer of semiconductive material; b. forming a resist pattern on said insulating coating; c. removing selected regions of said insulating coating which are exposed by openings in said resist pattern, thereby exposing an area or areas of said semiconductive layer; d. accelerating dopant ions into said exposed area or areas of said semiconductive layer and into the crystal lattice of said semiconductive layer to alter the conductivity thereof and to form planar P-N junctions in said semiconductive layer wherein said junctions terminate at said surface under said insulating coating; e. depositing metalization on the exposed surface area of said resist pattern and into contact with the exposed area or areas of said semiconductive layer to thereby make electrical contact to said P-N junctions, and thereafter f. removing said resist pattern from said insulating coating to thereby simultaneously remove the portion of said metalizatioN layer overlying said resist pattern, leaving intact the metalization in electrical contact with said semiconductive layer, whereby the ion implantation temperatures utilized during the acceleration of dopant ions into the semiconductor crystal lattice are insulfficient to deleteriously affect said resist pattern.
Claim 3
Dependent Claim
45 words
The process defined in claim 1 wherein said semiconductive layer is formed by the epitaxial deposition of a relatively high resistivity epitaxial layer on a relatively low resistivity substrate, whereby said substrate may be utilized to make good ohmic electrical contact to metalization applied thereto.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-01-06 | 1978-07-08 | 1979-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-01-06 | 1982-07-08 | 1983-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-01-06 | 1986-07-08 | 1987-01-07 | $7700.00 | Window Closed / Lapsed |