US3851161A
Expired / Lapsed
US
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Continuity network testing and fault isolating
Assignee: Unisys Corp
•
Filing: 1973-05-07
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Granted: 1974-11-26
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Expires: 1993-05-07
Abstract
Abstract A technique is provided for testing a circuit network having a plurality of circuit nodes which can be considered to lie in an ordered array of addresses. Such a technique is suitable for testing printed circuit boards and the like for continuity of desired circuits and absence of short circuiting. A circuit network is fitted into a test jig so that electrical contact is made to all circuit nodes. A test signal is applied to one of the circuit nodes and its presence or absence is simultaneously detected on all circuit nodes. The highest order addresss where the test signal appears is compared with the address of the node on which the signal is applied. If the detected addresss is higher a true signal is generated, and if it is not higher a false signal is generated. This procedure is repeated by applying the test signal to each circuit node in the network. The true and false signals generated are compared with recorded signals from a similar network known to be acceptable and any discrepancy indicates a defective network. Absence of a discrepancy indicates an acceptable network. Comparison of signals indicates the nature and general location of a defect in the network.
Inventors
- 👤 A Sloop
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 23:25
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2801; G01R31/2805
Claims Analysis
Total Claims: 54
Claim 1
Independent Claim
90 words
A method of testing a circuit network having a plurality of circuit nodes having an ordered array of addresses some of which circuit nodes may be electrically interconnected comprising the steps of: applying a test signal to one circuit node having a selected address; detecting the presence or absence of the test signal on all circuit nodes simultaneously; and determining the address of the highest order circuit node on which the test signal appears, thereby identifying the highest order circuit node to which said one circuit node is electrically connected.
Claim 2
Independent Claim
90 words
A method of testing a circuit network having a plurality of circuit nodes having an ordered array of addresses some of which circuit nodes may be electrically interconnected comprising the steps of: applying a test signal to one circuit node having a selected address; detecting the presence or absence of the test signal on all circuit nodes simultaneously; and determining the address of the highest order circuit node on which the test signal appears, thereby identifying the highest order circuit node to which said one circuit node is electrically connected.
Claim 3
Dependent Claim
48 words
A method of testing as defined in claim 1 further comprising the step of: comparing the address of the highest order node on which the signal appears with a recorded highest order address for the respective one circuit node in a similar circuit network known to be acceptable.
Claim 4
Dependent Claim
73 words
A method of testing as defined in claim 1 further comprising the steps of: comparing the address of the highest order node on which the signal appears with the address of the one circuit node to which the signal is applied for generating a first comparison signal; and comparing the first comparison signal with a recorded comparison signal for the respective one circuit node in a similar circuit network known to be acceptable.
Claim 5
Dependent Claim
72 words
A method of testing as defined in claim 3 further comprising the steps of: generating a ''''rejection'''' signal if the determined highest order address is different from the recorded highest order address for at least one node in the circuit network; and generating a ''''pass'''' signal if the determined highest order addresses for each node are the same as the corresponding recorded highest order addresses for all nodes in the circuit network.
Claim 6
Dependent Claim
71 words
A method of testing as defined in claim 3 further comprising the steps of: generating a ''''short'''' signal if the determined highest order address is higher than the corresponding recorded highest order address for at least one node in the circuit network; and generating an ''''open'''' signal if the determined highest order adDress is lower than the corresponding recorded highest order address for at least one node in the circuit network.
Claim 7
Independent Claim
81 words
A method of testing a circuit network having a plurality of circuit nodes having an ordered array of addresses comprising the steps of: applying a test signal to one circuit node having a selected address; detecting the presence or absence of the test signal on all circuit nodes simultaneously; and distinguishing whether the highest order address on which the test signal appears is the same as or greater than the address of the node on which the test signal is applied.
Claim 8
Independent Claim
81 words
A method of testing a circuit network having a plurality of circuit nodes having an ordered array of addresses comprising the steps of: applying a test signal to one circuit node having a selected address; detecting the presence or absence of the test signal on all circuit nodes simultaneously; and distinguishing whether the highest order address on which the test signal appears is the same as or greater than the address of the node on which the test signal is applied.
Claim 9
Dependent Claim
57 words
A method as defined in claim 6 further comprising the step of: repeating the detecting, determining and distinguishing steps while repeating the applying step with respect to each circuit node in the array; comparing the results of the plurality of distinguishing steps with the results of similar steps on a like circuit network known to be acceptable.
Claim 10
Independent Claim
153 words
A method of testing a network having a plurality of circuit nodes having an ordered array of addresses (A) comprising the steps of: a. applying a test signal to a circuit node having a selected address (A1); b. detecting the highest order circuit node on which the test signal appears; c. comparing the address (A2) of the highest order circuit node on which the signal is detected with the address A1 of the circuit node to which the signal is applied; d. generating a first state of comparison signal C1 if A2 is greater than A1 and a second state of comparison signal C1 if A2 is not greater than A1; e. scanning the test signal over all of the circuit nodes in the network and repeating steps (a) through (d) for each; and f. comparing the comparison signals C1 with respective comparison signals C2 from a similar network known to be acceptable.
Claim 11
Independent Claim
153 words
A method of testing a network having a plurality of circuit nodes having an ordered array of addresses (A) comprising the steps of: a. applying a test signal to a circuit node having a selected address (A1); b. detecting the highest order circuit node on which the test signal appears; c. comparing the address (A2) of the highest order circuit node on which the signal is detected with the address A1 of the circuit node to which the signal is applied; d. generating a first state of comparison signal C1 if A2 is greater than A1 and a second state of comparison signal C1 if A2 is not greater than A1; e. scanning the test signal over all of the circuit nodes in the network and repeating steps (a) through (d) for each; and f. comparing the comparison signals C1 with respective comparison signals C2 from a similar network known to be acceptable.
Claim 12
Dependent Claim
62 words
A method of testing as defined in claim 8 wherein the step of comparing comprises: reducing the sequence of comparison signals C1 to a number having fewer bits than the number of circuit nodes in the network; and comparing the reduced number with a recorded number similarly reduced from a sequence of comparison signals from a similar network known to be acceptable.
Claim 13
Dependent Claim
66 words
A method of testing as defined in claim 8 wherein the step of comparing comprises: comparing each comparison signal C1 from step (d) with a corresponding recorded comparison signal C2 from a similar network known to be acceptable; generating a pass signal in response to equality of all corresponding comparison signals, respectively; and generating a rejection signal in response to any discrepancy between corresponding comparison signals.
Claim 14
Dependent Claim
69 words
A method of testing as defined in claim 10 wherein the step of generating a rejection signal comprises: generating a ''''short'''' signal in response to a present comparison signal C1 indicating a higher order address A2 than the corresponding recorded comparison signal C2; and generating an ''''open'''' signal in response to a present comparison signal C1 indicating a lower order address A2 than the corresponding recorded comparison signal C2.
Claim 15
Dependent Claim
56 words
A method of testing as defined in claim 11 further comprising the step of: stopping the scanning of the test signal when a rejection signal is sensed; and displaying or recording the address of the node to which the test signal is then applied and the highest order address on which the test signal then appears.
Claim 16
Dependent Claim
50 words
A method of testing as defined in claim 8 wherein the detecting step comprises: sensing the presence or absence of the test signal on all circuit nodes simultaneously; and inhibiting any lower order address signals with a signal generated in response to the test signal on the highest order address.
Claim 17
Independent Claim
92 words
A method of mapping or listing circuits in a circuit network having a plurality of circuit nodes having an ordered array of addresses comprising the steps of: applying a test signal to a circuit node having a selected address; identifying the address of only the highest order circuit node on which the test signal appears; repeating the applying and identifying steps for each circuit node in the network for identifying the highest order address connected to each node, respectively; and listing all circuit nodes connected to each identified highest order node respectively.
Claim 18
Independent Claim
92 words
A method of mapping or listing circuits in a circuit network having a plurality of circuit nodes having an ordered array of addresses comprising the steps of: applying a test signal to a circuit node having a selected address; identifying the address of only the highest order circuit node on which the test signal appears; repeating the applying and identifying steps for each circuit node in the network for identifying the highest order address connected to each node, respectively; and listing all circuit nodes connected to each identified highest order node respectively.
Claim 19
Dependent Claim
51 words
A method of testing a circuit network comprising the steps defined in claim 14 and further comprising the step of: comparing the highest order addresses identified for each circuit node respectively with a corresponding, previously recorded, highest order address from a circuit network known to be acceptable, for detecting discrepancies therebetween.
Claim 20
Dependent Claim
89 words
Apparatus for testing a circuit network having a plurality of circuit nodes having an ordered array of addresses some of which circuit nodes may be electrically interconnected comprising: means for applying a test signal to one circuit node having a selected address; means for detecting the presence or absence of test signal on all circuit nodes simultaneously; and means for determining the address of the highest order circuit node on which the test signal appears which is the highest order circuit node electrically connected to the one circuit node.
Claim 21
Dependent Claim
89 words
Apparatus for testing a circuit network having a plurality of circuit nodes having an ordered array of addresses some of which circuit nodes may be electrically interconnected comprising: means for applying a test signal to one circuit node having a selected address; means for detecting the presence or absence of test signal on all circuit nodes simultaneously; and means for determining the address of the highest order circuit node on which the test signal appears which is the highest order circuit node electrically connected to the one circuit node.
Claim 22
Dependent Claim
46 words
Testing apparatus as defined in claim 16 further comprising: means for comparing the address of the highest order node on which the signal appears with a recorded highest order address for the respective one one circuit node in a similar circuit network known to be acceptable.
Claim 23
Dependent Claim
72 words
Testing apparatus as defined in claim 16 further comprising: means for comparing the address of the highest order node on which the signal appears with the address of the one circuit node to which the signal is applied for generating a first comparison signal; and means for comparing the first comparison signal with a recorded comparison signal for the respective one circuit node in a similar circuit network known to be acceptable.
Claim 24
Dependent Claim
70 words
Testing apparatus as defined in claim 18 further comprising: means for generating a ''''short'''' signal if the determined highest order address is higher than the corresponding recorded highest order address for at least one node in the circuit network; and means for generating an ''''open'''' signal if the determined highest order address is lower than the corresponding recorded highest order address for at least one node in the circuit network.
Claim 25
Dependent Claim
71 words
Testing apparatus as defined in claim 18 further comprising: means for generating a ''''rejection'''' signal if the determined highest order address is different from the recorded highest order address for at least one node in the circuit network; and means for generating a ''''pass'''' signal if the determined highest order addresses for each node are the same as the corresponding recorded highest order addresses for all nodes in the circuit network.
Claim 26
Dependent Claim
83 words
Apparatus for testing a circuit network having a plurality of circuit nodes having an ordered array of addresses comprising: means for applying a test signal to one circuit node having a selected address; means for detecting the presence or absence of the test signal on all circuit nodes simultaneously; and means for distinguishing whether the highest order address on which the test signal appears is the same as or greater than the address of the node on which the test signal is applied.
Claim 27
Dependent Claim
83 words
Apparatus for testing a circuit network having a plurality of circuit nodes having an ordered array of addresses comprising: means for applying a test signal to one circuit node having a selected address; means for detecting the presence or absence of the test signal on all circuit nodes simultaneously; and means for distinguishing whether the highest order address on which the test signal appears is the same as or greater than the address of the node on which the test signal is applied.
Claim 28
Dependent Claim
58 words
Testing apparatus as defined in claim 21 further comprising: means for repeating the detecting, determining and distinguishing steps while repeating the applying step with respect to each circuit node in the array; means for comparing the results of the plurality of distinguishing steps with the results of simIlar steps on a like circuit network known to be acceptable.
Claim 29
Dependent Claim
155 words
Apparatus for testing a network having a plurality of circuit nodes having an ordered array of addresses (A) comprising: means for applying a test signal to a circuit node having a selected address (A1); means for detecting the highest order circuit node on which the test signal appears; means for comparing the address (A2) of the highest order circuit node on which the signal is detected with the address A1 of the circuit node to which the signal is applied; means for generating a first comparison signal if A2 is greater than A1 and a second comparison signal if A2 is not greater than A1; means for repeatedly applying the test signal to each of the circuit nodes in the network and generating a series of comparison signals corresponding to each; and means for comparing the series of comparison signals with s second series of comparison signals from a similar network known to be acceptable.
Claim 30
Dependent Claim
155 words
Apparatus for testing a network having a plurality of circuit nodes having an ordered array of addresses (A) comprising: means for applying a test signal to a circuit node having a selected address (A1); means for detecting the highest order circuit node on which the test signal appears; means for comparing the address (A2) of the highest order circuit node on which the signal is detected with the address A1 of the circuit node to which the signal is applied; means for generating a first comparison signal if A2 is greater than A1 and a second comparison signal if A2 is not greater than A1; means for repeatedly applying the test signal to each of the circuit nodes in the network and generating a series of comparison signals corresponding to each; and means for comparing the series of comparison signals with s second series of comparison signals from a similar network known to be acceptable.
Claim 31
Dependent Claim
63 words
Testing apparatus as defined in claim 23 wherein the means for comparing comprises: means for reducing the sequence of comparison signals to a number having fewer bits than the number of circuit nodes in the network; and means for comparing the reduced number with a recorded number similarly reduced from a sequence of comparison signals from a similar network known to be acceptable.
Claim 32
Dependent Claim
70 words
Testing apparatus as defined in claim 23 wherein the means for comparing comprises: means for comparing each comparison signal in the first series with the corresponding recorded comparison signal in the second series; means for generating a pass signal in response to equality of all corresponding comparison signals in the two series; and generating a failure signal in response to any discrepancy between corresponding comparison signals in the two series.
Claim 33
Dependent Claim
67 words
Testing apparatus as defined in claim 25 wherein the means for generating a failure signal comprises: means for generating a ''''short'''' signal in response to a present comparison signal indicating a higher order address A2 than the corresponding recorded comparison signal; and means for generating an ''''open'''' signal in response to a present comparison signal indicating a lower order address A2 than the corresponding recorded comparison signal.
Claim 34
Dependent Claim
55 words
Testing apparatus as defined in claim 26 further comprising: means for stopping the scanning of the test signal when a rejection signal is sensed; and means for displaying or recording the address of the node to which the test signal is then applied and the highest order address on which the test signal then appears.
Claim 35
Dependent Claim
53 words
Testing apparatus as defined in claim 23 wherein the means for detecting comprises: means for sensing the presence or absence of the test signal on all circuit nodes simultaneously; and means for inhibiting any lower order address signals with a signal generated in response to the test signal on the highest order address.
Claim 36
Dependent Claim
93 words
Apparatus for listing circuits in a circuit network having a plurality of circuit nodes having an ordered array of addresses comprising: means for applying a test signal to a circuit node having a selected address; means for identifying the address of only the highest order circuit node on which the test signal appears; means for repeating the applying and identifying steps for each circuit node in the network for identifying the highest order address connected to each node; and means for listing all circuit nodes connected to each identified highest order node respectively.
Claim 37
Dependent Claim
93 words
Apparatus for listing circuits in a circuit network having a plurality of circuit nodes having an ordered array of addresses comprising: means for applying a test signal to a circuit node having a selected address; means for identifying the address of only the highest order circuit node on which the test signal appears; means for repeating the applying and identifying steps for each circuit node in the network for identifying the highest order address connected to each node; and means for listing all circuit nodes connected to each identified highest order node respectively.
Claim 38
Dependent Claim
46 words
Apparatus as defined in claim 29 further comprising: means for comparing the highest order addresses identified for each circuit node respectively with a corresponding, previously recorded, highest order address for each circuit node respectively from a circuit network known to be acceptable, for dEtecting discrepancies therebetween.
Claim 39
Dependent Claim
77 words
Apparatus as defined in claim 29 further comprising: means for comparing the address of the highest order circuit node on which the test signal appears with the address of the circuit node having the selected address for generating a first comparison signal; and means for comparing the first comparison signal with a recorded comparison signal for the respective circuit node having the selected address in a similar circuit network known to be acceptable for detecting discrepancies therebetween.
Claim 40
Dependent Claim
110 words
Apparatus for testing a circuit network having a plurality of circuit nodes having an ordered array of addresses A comprising: means for applying a test signal to a circuit node having a selected address A1; means for simultaneously detecting the presence or absence of the test signal on all other nodes in the network; means for distinguising the address A2 of the highest order node on which the test signal is present; means for generating a first comparison signal if A2 is greater than A1, and a second comparison signal if A2 is not greater than A1; and means for comparing the generated comparison signal with a recorded comparison signal.
Claim 41
Dependent Claim
110 words
Apparatus for testing a circuit network having a plurality of circuit nodes having an ordered array of addresses A comprising: means for applying a test signal to a circuit node having a selected address A1; means for simultaneously detecting the presence or absence of the test signal on all other nodes in the network; means for distinguising the address A2 of the highest order node on which the test signal is present; means for generating a first comparison signal if A2 is greater than A1, and a second comparison signal if A2 is not greater than A1; and means for comparing the generated comparison signal with a recorded comparison signal.
Claim 42
Dependent Claim
108 words
Apparatus for testing a circuit network having a plurality of circuit nodes with an ordered array of addresses some of which circuit nodes may be electrically interconnected comprising: means for applying a test signal to a circuit node having a selected address; means for simultaneously detecting the presence or absence of the test signal on each circuit node in the array; means for distinguishing the highest order node on which the test signal is present from all other circuit nodes; and means for comparing the address of the highest order node so distinguished with a desired highest order address for the node to which the signal is applied.
Claim 43
Dependent Claim
108 words
Apparatus for testing a circuit network having a plurality of circuit nodes with an ordered array of addresses some of which circuit nodes may be electrically interconnected comprising: means for applying a test signal to a circuit node having a selected address; means for simultaneously detecting the presence or absence of the test signal on each circuit node in the array; means for distinguishing the highest order node on which the test signal is present from all other circuit nodes; and means for comparing the address of the highest order node so distinguished with a desired highest order address for the node to which the signal is applied.
Claim 44
Independent Claim
246 words
An apparatus for testing a circuit network having a plurality of circuit nodes having an ordered array of addresses some of which circuit nodes may be electrically interconnected comprising: a decoder having a binary address signal input and an ordered plurality of outputs for applying a test signal to any one output corresponding to an address signal input; a priority encoder network having a plurality of inputs each connected to an output of the decoder and a binary address signal output for generating a binary output address signal corresponding to the highest order input on which a test signal appears; a circuit test jig having a plurality of contacts each connected to an output of the decoder and an input to the encoder for applying a test signal to any circuit node of an arbitrary circuit network inserted therein and for receiving a test signal from any circuit node of the network; receiving a test signal from any circuit node of the network; and an address comparator connected to the address signal input to the decoder and to the address signal output of the encoder and having a binary output line for generating a first comparison signal having a first binary output state if an address on the address signal output is greater than an address on the address signal input, and a second binary output state if an address on the address signal output is not greater than an address on the address signal input.
Claim 45
Independent Claim
246 words
An apparatus for testing a circuit network having a plurality of circuit nodes having an ordered array of addresses some of which circuit nodes may be electrically interconnected comprising: a decoder having a binary address signal input and an ordered plurality of outputs for applying a test signal to any one output corresponding to an address signal input; a priority encoder network having a plurality of inputs each connected to an output of the decoder and a binary address signal output for generating a binary output address signal corresponding to the highest order input on which a test signal appears; a circuit test jig having a plurality of contacts each connected to an output of the decoder and an input to the encoder for applying a test signal to any circuit node of an arbitrary circuit network inserted therein and for receiving a test signal from any circuit node of the network; receiving a test signal from any circuit node of the network; and an address comparator connected to the address signal input to the decoder and to the address signal output of the encoder and having a binary output line for generating a first comparison signal having a first binary output state if an address on the address signal output is greater than an address on the address signal input, and a second binary output state if an address on the address signal output is not greater than an address on the address signal input.
Claim 46
Dependent Claim
109 words
An apparatus as defined in claim 34 further comprising: a memory for storing a plurality of second comparison signals in an ordered array corresponding to a series of binary addresses and reading one of said second comparison signals in response to a binary input address signal; an address control connected to the decoder and to the memory for applying a binary input address signal to both; means connected to the address comparator and the memory for comparing the first comparison signal corresponding to an input address with the second comparison signal corresponding to the same input address and generating an output signal if the comparison signals are not equal.
Claim 47
Dependent Claim
65 words
An apparatus as defined in claim 35 wherein the means for comparing comprises: a comparator providing a first output signal if the binary state of the first comparison signal is greater than the binary state of the second comparison signal, and a second output signal if the binary state of the second comparison signal is greater than the binary state of the first comparison signal.
Claim 48
Dependent Claim
31 words
An apparatus as defined in claim 35 further comprising: means for recording the input address and the output address for each input address for which the comparison signals are not equal.
Claim 49
Dependent Claim
145 words
Apparatus for testing a circuit network having a plurality of circuit nodes with an ordered array of addresses some of which circuit nodes may be electrically interconnected comprising: means for applying a test signal to a circuit node having a selected address; means for simultaneously detecting the presence or absence of the test signal on each circuit node in the array; means for distinguishing the highest order node on which the test signal is present from all other circuit nodes; means for comparing the address of the highest order circuit node on which the test signal is present with the address of the circuit node to which the signal is applied for generating a first comparison signal; and means for comparing the first comparison signal with a recorded comparison signal for the same circuit node respectively in a similar circuit network known to be acceptable.
Claim 50
Dependent Claim
145 words
Apparatus for testing a circuit network having a plurality of circuit nodes with an ordered array of addresses some of which circuit nodes may be electrically interconnected comprising: means for applying a test signal to a circuit node having a selected address; means for simultaneously detecting the presence or absence of the test signal on each circuit node in the array; means for distinguishing the highest order node on which the test signal is present from all other circuit nodes; means for comparing the address of the highest order circuit node on which the test signal is present with the address of the circuit node to which the signal is applied for generating a first comparison signal; and means for comparing the first comparison signal with a recorded comparison signal for the same circuit node respectively in a similar circuit network known to be acceptable.
Claim 51
Independent Claim
81 words
A method of testing a circuit network having a plurality of circuit nodes having an ordered array of addresses comprising the steps of: applying a test signal to one circuit node having a selected address; detecting the presence or absence of the test signal on all circuit nodes simultaneously; and determining the presence or absence of a circuit node on which the test signal appears having a higher order address than the circuit node to which the test signal is applied.
Claim 52
Independent Claim
81 words
A method of testing a circuit network having a plurality of circuit nodes having an ordered array of addresses comprising the steps of: applying a test signal to one circuit node having a selected address; detecting the presence or absence of the test signal on all circuit nodes simultaneously; and determining the presence or absence of a circuit node on which the test signal appears having a higher order address than the circuit node to which the test signal is applied.
Claim 53
Dependent Claim
83 words
Apparatus for testing a circuit network having a plurality of circuit nodes having an ordered array of addresses comprising: means for applying a test signal to one circuit node having a selected address; means for detecting the presence or absence of the test signal on all circuit nodes simultaneously; and means for determining the presence or absence of a circuit node on which the test signal appears having a higher order address than the circuit node to which the test signal is applied.
Claim 54
Dependent Claim
83 words
Apparatus for testing a circuit network having a plurality of circuit nodes having an ordered array of addresses comprising: means for applying a test signal to one circuit node having a selected address; means for detecting the presence or absence of the test signal on all circuit nodes simultaneously; and means for determining the presence or absence of a circuit node on which the test signal appears having a higher order address than the circuit node to which the test signal is applied.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-25 | 1978-05-27 | 1978-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-25 | 1982-05-27 | 1982-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-25 | 1986-05-27 | 1986-11-26 | $7700.00 | Window Closed / Lapsed |