Testing and addressing apparatus for an array of circuit elements

Abstract

Abstract 1,206,521. Programmed control of testing. INTERNATIONAL BUSINESS MACHINES CORP. Jan.10, 1968 [Jan.13, 1967], No.1370/68. Heading G3N. [Also in Division G1] A circuit tester for testing an ordered array of electric terminals comprises first and second test terminals and an addressings arrangement for connecting a prespecified terminal of the array to the first test terminal all terminals of lower order than the prespecified terminal simultaneously to the second test terminal, where lower order is defined as follows:- if all the terminals have addresses in the form of X, Y co-ordinates, then for any terminal P o having co-ordinates X o Y o , lower order terminals are those for which YLYo and X takes any value, and those for which Y=Yo and X < X o . In testing a network of terminals 2-5, Fig. 2a for short circuits to other terminals on the array, the lowest order terminal in the network, terminal 002,013 Fig. 2 is connected to one side of a test unit 8, Fig.1, and all its lower order terminals are connected simultaneously to the other terminal of the unit 8; this unit then tests for short circuits under the control of a control unit 3. The terminals of the array are grouped into RATS (each RAT comprising 12 rows of terminals) and PACS (each PAC comprising 12 columns of terminals) and if a short circuit is found the control unit 3 locates the faulty lower order terminal by scanning those terminals first in RATS, then rows in the faulty RAT, then in PACS and finally in columns. After locating the faulty terminal the scan is continued to determine if there are any other short circuits. In testing the network for open circuits, the lowest order terminal is connected to one side of test unit 8 and the second terminal (030, 032) to the other side of unit 8, the open circuit test then being carried out. Then the third terminal (072, 048) is connected to the unit 8 in place of the lowest order terminal and the test repeated. Then the fourth terminal (090, 084) is connected to unit 8 in place of the second terminal, and so on, until the continuity test is completed. The control unit 3 includes an instruction and storage unit 4, Fig. 1b (not shown) which receives from a computer or tape drive (11) information as to the addresses (X, Ycoordinates) of the terminals to be tested and the type of test to be carried out. The unit 3 further includes a scan control arrangement (5) for scanning the terminals, and in addition controls selection matrices 6, 9 and 7,10 which connect the individual terminals to the test unit.

Inventors

• 👤 Jack P Bennett
• 👤 Charles A Harring
• 👤 William Teo

Bibliographic Details