Cache store clearing operation for multiprocessor mode

Claim 2

A clearing apparatus for a cache store located in each processor of a multiprocessor data processing system, said clearing apparatus of each cache comprising: addressable storage units one associated with each column of a set associative, multi-level, multi-column addressable tag directory to its related cache store and activated by alike address signals as its associated column, each storage unit when set storing full/empty status indicator signals of each level of its associated column; a count means connected to receive the status indicator signals from each storage unit for directing its output to said storage units for storage therein, said count means incrementing the status indicator signals when each storage unit is addressed by its address signals; said storage units indicating valid data in its related cache store by the count status of said storage units in that levels lower than the level indicated by the status indicator signals points to valid data in the cache store and levels higher point to invalid data, with at least one status indicator signal indicating that all levels are full and contain valid data; and clearing means connected to said count means and said storage units for resetting the status indicating signals, said clearing means activated by an initiate clear signal generated by a signal allowing peripheral access to said data processing system and by a signal from its associated processor signifying access allowed through a gate into a restricted area of a main memory store of the data processing system.

Claim 3

A clearing apparatus as defined in claim 1 wherein the tag directory includes four levels for each column and each of said storage units stores three bits of information, two for the level count and one for the level full status indication.

Claim 4

A clearing apparatus as defined in claim 1 wherein said clearing means includes: a pulse generator actuated by said initiate clear signal for generating a burst of pulses; and a counting circuit connected to receive and increment said burst of pulses for generating clearing address signals, said clearing address signals actuating said storage units in turn according to said counting circuit; said initiate clear signal inhibiting said count means.

Claim 5

A clearing apparatus as defined by claim 3 wherein said initiate clear signal actuates several storage units at one time by activating an address decoder generating a chip address signal providing the highest order decoded address signals to said storage units.

Claim 6

A clearing apparatus for a processor contained cache store section in a multiprocessor data processing system with each processor including its own cache store section, said data processing system including a main addressable memory store having a gate to prevent more than one processor from gaining access to restricted areas of said main memory store, an I/O controller controlling peripheral access to the data processing system, and a system controller controlling communication among said plurality of processors, said I/O controller and said main memory store, each of said cache store sections including an addressable cache store, a tag directory addressable store associated to said cache store, said tag directory having a plurality of columns addressed by high order address signals with each column having a plurality of levels, each of said levels storing low order address signals pointing to data information in said cache store, and a level selector controlling storage into the levels of said tag directory, said clearing apparatus comprising: addressable storage units, one associated with each tag directory column and actuated by the same address signals, each storage uniT when set storing full/empty status indicator signals of each level of its associated column; a count means connected to receive the status indicator signals from each storage unit for directing its output to said storage units for storage therein, said count means incrementing the status indicator signals when each storage unit is addressed by its address signals; said storage units indicating valid data in its related cache store by the count status of said storage units in that levels lower than the level indicated by the status indicator signals points to valid data in the cache store and levels higher point to invalid data, with at least one status indicator signal indicating that all levels are full and contain valid data; and clearing means connected to said count means and said storage units for resetting the status indicating signals, said clearing means activated by an initiate clear signal generated by a signal generated by the I/O controller allowing peripherals access to said data processing systems and by a signal from its associated processor signifying access allowed through the gate into the restricted areas of the main memory store.

Claim 7

A clearing apparatus for a processor contained cache store section in a multiprocessor data processing system with each processor including its own cache store section, said data processing system including a main addressable memory store having a gate to prevent more than one processor from gaining access to restricted areas of said main memory store, an I/O controller controlling peripheral access to the data processing system, and a system controller controlling communication among said plurality of processors, said I/O controller and said main memory store, each of said cache store sections including an addressable cache store, a tag directory addressable store associated to said cache store, said tag directory having a plurality of columns addressed by high order address signals with each column having a plurality of levels, each of said levels storing low order address signals pointing to data information in said cache store, and a level selector controlling storage into the levels of said tag directory, said clearing apparatus comprising: addressable storage units, one associated with each tag directory column and actuated by the same address signals, each storage uniT when set storing full/empty status indicator signals of each level of its associated column; a count means connected to receive the status indicator signals from each storage unit for directing its output to said storage units for storage therein, said count means incrementing the status indicator signals when each storage unit is addressed by its address signals; said storage units indicating valid data in its related cache store by the count status of said storage units in that levels lower than the level indicated by the status indicator signals points to valid data in the cache store and levels higher point to invalid data, with at least one status indicator signal indicating that all levels are full and contain valid data; and clearing means connected to said count means and said storage units for resetting the status indicating signals, said clearing means activated by an initiate clear signal generated by a signal generated by the I/O controller allowing peripherals access to said data processing systems and by a signal from its associated processor signifying access allowed through the gate into the restricted areas of the main memory store.

Claim 8

A clearing apparatus as defined in claim 5 wherein said clearing means includes: a pulse generator actuated by said initiate clear signal for generating a burst of pulses; and a counting circuit connected to receive and increment said burst of pulses for generating clearing address signals, said clearing address signals actuating said storage units in turn according to said counting circuit; said initiate clear signal inhibiting said count means.

Claim 9

A clearing apparatus as defined by claim 6 wherein said initiate clear signal actuates several storage units at one time by actuating an address decoder generating a chip address signal providing the highest order decoded address signals to said storage units.

Claim 10

A processor controlled cache store storing data information from a main memory store in addressable areas and located in each processor of a multiprocessor data processing system, said cache store comprising: a tag directory addressable associated store having a plurality of columns with each column having a plurality of levels, said tag directory storing low order address signals in each level pointing to data information stored in said cache store with each column addressed by high order address signals; a comparator having a plurality of comparing means arranged in groups, one group for each level of said tag directory, said comparator connected to receive the high order address signals of data information requested by its processor and for comparing these high order address signals with the high order address signals retrieved from each level of the column addressed by the low order address signals and received from the tag directory, said comparator generating on a correct comparison a match signal signifying that the data information is in the cache store and a portion of the cache address signal; addressable storage units, one associated with each tag directory column, addressable by the same low order address signal as its associated column, each of said storage units storing a full/empty status indicator of each level of its associated column; a count means connected to receive the status indicator signals from each storage unit for directing its output to said storage units for storage therein, said count means incrementing the status indicator signals when each storage unit is addressed by its address signals; a level selector connected to receive the full/empty status indicators and the high order address signals for entering the high order address signals into the level of the addressed column according to the full/empty status indicator using a round robin organization, said full/empty status indicator of the addressed column also applied to said comparator to control said comparator such that valid data in said cache store is indicateD by the count status of said storage unit in that levels lower than the level indicated by the status indicator signal points to valid data in the cache store and levels higher point to invalid data, with at least one status indicator signal indicating that all levels are full and contain valid data; and clearing means connected to said count means and said storage units for resetting the status indicating signals, said clearing means activated by an initiate clear signal generated by a signal allowing peripherals access to said data processing system and by a signal from its associated processor signifying access allowed through a gate into a restricted area of a main memory store of the data processing system.

Claim 11

A processor controlled cache store storing data information from a main memory store in addressable areas and located in each processor of a multiprocessor data processing system, said cache store comprising: a tag directory addressable associated store having a plurality of columns with each column having a plurality of levels, said tag directory storing low order address signals in each level pointing to data information stored in said cache store with each column addressed by high order address signals; a comparator having a plurality of comparing means arranged in groups, one group for each level of said tag directory, said comparator connected to receive the high order address signals of data information requested by its processor and for comparing these high order address signals with the high order address signals retrieved from each level of the column addressed by the low order address signals and received from the tag directory, said comparator generating on a correct comparison a match signal signifying that the data information is in the cache store and a portion of the cache address signal; addressable storage units, one associated with each tag directory column, addressable by the same low order address signal as its associated column, each of said storage units storing a full/empty status indicator of each level of its associated column; a count means connected to receive the status indicator signals from each storage unit for directing its output to said storage units for storage therein, said count means incrementing the status indicator signals when each storage unit is addressed by its address signals; a level selector connected to receive the full/empty status indicators and the high order address signals for entering the high order address signals into the level of the addressed column according to the full/empty status indicator using a round robin organization, said full/empty status indicator of the addressed column also applied to said comparator to control said comparator such that valid data in said cache store is indicateD by the count status of said storage unit in that levels lower than the level indicated by the status indicator signal points to valid data in the cache store and levels higher point to invalid data, with at least one status indicator signal indicating that all levels are full and contain valid data; and clearing means connected to said count means and said storage units for resetting the status indicating signals, said clearing means activated by an initiate clear signal generated by a signal allowing peripherals access to said data processing system and by a signal from its associated processor signifying access allowed through a gate into a restricted area of a main memory store of the data processing system.

Claim 12

A processor controlled cache store as defined in claim 8 wherein said clearing means includes: a pulse generator actuated by said initiate clear signal for generating a burst of pulses; and a counting circuit connected to receive and increment said burst of pulses for generating clearing address signals, said clearing address signals actuating said storage units in turn according to said counting circuit; said initiate clear signal inhibiting said count means.

Claim 13

A processor controlled cache store as defined by claim 9 wherein said initiate clear signal actuates several storage units at one time by actuating an address decoder generating a chip address signal providing the highest order decoded address signals to said storage units.

Claim 14

In a data processing system including a plurality of processors, a main memory store storing data information is addressable locations and including a gate to prevent more than one processor from gaining access to restricted areas of said main memory store, an I/O controller controlling peripheral access to the data processing system, and a system controller controlling communication among said plurality of processors, said I/O controller, and said main memory store, wherein each of said plurality of processors includes a cache section comprising: a cache store storing data information in addressable locations; a tag directory addressable associated store having a plurality of columns with each column having a plurality of levels, said tag directory storing low order address signals in each level pointing to data information stored in said cache store with each column addressed by high order address signals; a comparator having a plurality of comparing means arranged in groups, one group for each level of said tag directory, said comparator connected to receive the high order address signals of data information requested by its processor and for comparing these high order address signals with the high order address signals retrieved from each level of the column addressed by the low order address signals and received from the tag directory, said comparator generating on a correct comparison a match signal signifying that the data information is in the cache store and a portion of the cache address signal; addressable storage units, one associated with each tag directory column, addressable by the same low order address signal as its associated column, each of said storage units storing a full/empty status indicator of each level of its associated column; a count means connected to receive the status indicator signals from each storage unit for directing its output to said storage units for storage therein, said count means incrementing the status indicator signals when each storage unit is addressed by its address signals; a level selector connected to receive the full/empty status indicators and the high order address signals for entering the high order address signals into the addressed column of said tag directory and to the level of the addressed column according to the full/empty status indicator using a round robin organization, said full/empty status indicator of the addressed column also applied to said comparator to control said comparator such that valid datA in said cache store is indicated by the count status of said storage unit in that levels lower than the level indicated by the status indicator signals points to valid data in the cache store and levels higher point to invalid data, with at least one status indicator signal indicating that all levels are full and contain valid data; and clearing means connected to said count means and said storage units for resetting the status indicating signals, said clearing means activated by an initiate clear signal generated by a signal allowing peripherals access to said processing system and by a signal from its associated processor signifying access allowed through a gate into a restricted area of a main memory store of the data processing system.

Claim 15

In a data processing system including a plurality of processors, a main memory store storing data information is addressable locations and including a gate to prevent more than one processor from gaining access to restricted areas of said main memory store, an I/O controller controlling peripheral access to the data processing system, and a system controller controlling communication among said plurality of processors, said I/O controller, and said main memory store, wherein each of said plurality of processors includes a cache section comprising: a cache store storing data information in addressable locations; a tag directory addressable associated store having a plurality of columns with each column having a plurality of levels, said tag directory storing low order address signals in each level pointing to data information stored in said cache store with each column addressed by high order address signals; a comparator having a plurality of comparing means arranged in groups, one group for each level of said tag directory, said comparator connected to receive the high order address signals of data information requested by its processor and for comparing these high order address signals with the high order address signals retrieved from each level of the column addressed by the low order address signals and received from the tag directory, said comparator generating on a correct comparison a match signal signifying that the data information is in the cache store and a portion of the cache address signal; addressable storage units, one associated with each tag directory column, addressable by the same low order address signal as its associated column, each of said storage units storing a full/empty status indicator of each level of its associated column; a count means connected to receive the status indicator signals from each storage unit for directing its output to said storage units for storage therein, said count means incrementing the status indicator signals when each storage unit is addressed by its address signals; a level selector connected to receive the full/empty status indicators and the high order address signals for entering the high order address signals into the addressed column of said tag directory and to the level of the addressed column according to the full/empty status indicator using a round robin organization, said full/empty status indicator of the addressed column also applied to said comparator to control said comparator such that valid datA in said cache store is indicated by the count status of said storage unit in that levels lower than the level indicated by the status indicator signals points to valid data in the cache store and levels higher point to invalid data, with at least one status indicator signal indicating that all levels are full and contain valid data; and clearing means connected to said count means and said storage units for resetting the status indicating signals, said clearing means activated by an initiate clear signal generated by a signal allowing peripherals access to said processing system and by a signal from its associated processor signifying access allowed through a gate into a restricted area of a main memory store of the data processing system.