Alterable read only memory organization

Claim 2

An alterable read only memory organization for data processing systems and the like comprising a master read only memory unit having a plurality of addresses for permanent storage of system data; an alterable read only memory unit for storage of altered system data, said alterable memory unit having a smaller number of addresses than said master memory unit; address means coupled to both of said memory units for causing said memory units to read out the data stored therein; and data select means coupled to each of said memory units for selecting the data read out from said alterable memory unit and inhibiting the data read out from said master memory unit whenever the data read out from said master memory unit is from an address for which altered data is stored in said alterable memory unit and for selecting the data read out from said master memory unit and inhibiting the data read out from said alterable memory unit whenever the data read out from said master memory unit is from an address for which no data is stored in said alterable memory uNit, wherein said data select means comprises a selectively operable first portion coupled between the output of each of said memory units and the output of said memory organization, and a second portion coupled to said first portion for control thereof.

Claim 3

An alterable read only memory organization for data processing systems and the like comprising a master read only memory unit having a plurality of addresses for permanent storage of system data; an alterable read only memory unit for storage of altered system data, said alterable memory unit having a smaller number of addresses than said master memory unit; address means coupled to both of said memory units for causing said memory units to read out the data stored therein; and data select means coupled to each of said memory units for selecting the data read out from said alterable memory unit and inhibiting the data read out from said master memory unit whenever the data read out from said master memory unit is from an address for which altered data is stored in said alterable memory unit and for selecting the data read out from said master memory unit and inhibiting the data read out from said alterable memory unit whenever the data read out from said master memory unit is from an address for which no data is stored in said alterable memory unit, wherein said data select means comprises selectively operable switch means coupled between the output of each of said memory units and the output of said memory organization, and address comparator means coupled to said switch means for control thereof, said address comparator means being operable to control said switch means in response to the presence or absence of a difference between the address of data read out of said master memory unit and the address of data read out of said alterable memory unit, so that when such difference is present the data appearing at the output of the memory organization is the data read out from said master memory unit and when such difference is not present the data at the output of the memory organization is the data read out from said alterable memory unit.

Claim 4

An alterable read only memory organization for data processing systems and the like comprising a master read only memory unit having a plurality of addresses for permanent storage of system data; an alterable read only memory unit for storage of altered system data, said alterable memory unit having a smaller number of addresses than said master memory unit; address means coupled to both of said memory units for causing said memory units to read out the data stored therein; and data select means coupled to each of said memory units for selecting the data read out from said alterable memory unit and inhibiting the data read out from said master memory unit whenever the data read out from said master memory unit is from an address for which altered data is stored in said alterable memory unit and for selecting the data read out from said master memory unit and inhibiting the data read out from said alterable memory unit whenever the data read out from said master memory unit is from an address for which no data is stored in said alterable memory unit, wherein said data select means comprises selectively operable switch means coupled between the output of each of said memory units and the output of said memory organization, and address comparator means coupled to said switch means for control thereof, said address comparator means being operable to control said switch means in response to the presence or absence of a difference between the address of data read out of said master memory unit and the address of data read out of said alterable memory unit, so that when such difference is present the data appearing at the output of the memory organization is the data read out from said master memory unit and when such difference is not present the data at the output of the memory organization is the data read out from said alterable memory unit.

Claim 5

An alterable read only memory organization as claimed in claim 2, wherein said alterable read only memory unit has a first section for storage of said altered system data and a second section for storage of the address data for such altered system data and wherein the addresses compared by said address comparator means are the addresses applied to said master memory unit and the addresses stored in said second section of the alterable memory unit.

Claim 6

An alterable read only memory organization as claimed in claim 3, wherein said address means comprises a first address counter coupled to said master memory unit for sequentially addressing said master memory unit and a second address counter coupled to both sections of said alterable memory unit for simultaneously addressing both of said sections.

Claim 7

An alterable read only memory organization as claimed in claim 4, wherein said address comparator means comprises a digital comparator having one input thereof coupled to the output of said first address counter, the other input thereof coupled to the output of said second section of said alterable memory unit, and the output thereof coupled to said second address counter and said selectively operable switch means, so that said second address counter is sequentially triggered to the next address whenever the altered system data stored in said alterable memory unit appears at the output of the memory organization.

Claim 8

An alterable read only memory organization as claimed in claim 5, wherein the sequential operating cycle of said second address counter is reset by the cyclic reset output of said first address counter.

Claim 9

An alterable read only memory organization as claimed in claim 6, wherein said alterable read only memory unit is an electrically alterable read only memory unit.

Claim 10

An alterable read only memory organization as claimed in claim 7, whErein said master read only memory unit comprises a plurality of replaceable read only memory modules, so that said alterable read only memory unit can be cleared of stored data when full and the altered system data stored therein transferred to one or more replacement modules for said master memory unit.