Maintenance control arrangement employing data lines for transmitting control signals to effect maintenance functions

Claim 1

In a communication switching system including a data processing unit having a central processor means, a registersender means, a memory means, means for reading out bits of stored information from said memory means, and register junctor means arranged on a time division multiplex basis for transferring information to said memory means during recurring pulses generated by a clock source, said pulses each defining a different time slot under control of a register multiplex unit, and a data bus connected between said central processor means and said register-sender means, a maintenance control arrangement comprising maintenance means including direct control logic means having a plurality of logic circuit means including logic circuit means individually connected to said register junctor means, and enable means connected to said clock source and responsive to a control pulse directive transmitted over said data bus from said central processor means to said direct control logic means for effecting the generation of an enabling signal for said logic circuit means of said direct control logic means during a predetermined time slot following the time slots associated with the register junctor means, said memory means having a plurality of data bit storage locations for storing direct control bits for indicating which of said logic circuit means of said direct control logic means are to be enabled, said means for reading out transferring the direct control bits stored in said memory means during said predetermined time slot to permit the indicated ones of said logic circuit means of said direct control logic means to be enabled, when said enabling signal is provided by said enable means during said predetermined time slot so as not to interfere with the operation of the register junctor means transferring information.