US3568153A
Expired / Lapsed
US
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Memory with error correction
Assignee: International Business Machines Corp
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Filing: 1968-09-16
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Granted: 1971-03-02
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Expires: 1988-09-16
Abstract
Abstract This invention relates to a memory for a data processing system in which the data stored in the memory is encoded to form check bits that permit identifying and correcting an error in a word of data read from the memory. The specification teaches improved circuits for changing the check bits to agree with a corrected word after an error has been detected and corrected.
Inventors
- 👤 Gerald W Kurtz
- 👤 August K Pattin Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 10:42
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
137 words
In a memory of the type having a fetch register arranged to receive a word from the memory, a store register adapted to receive a memory word to be restored in the memory or a new word to be stored or a word made up of bytes of a memory word to be restored and new bytes to be storeD; means responsive to the contents of said store register for generating an error correction code to be stored with the word in the store register, and means responsive to the contents of said fetch register for producing syndromes and means responsive to said syndromes for correcting an error in a word read from the memory and any corresponding error in the word or byte of a word to be restored in the memory, wherein the improvement comprises;
Claim 2
Dependent Claim
137 words
In a memory of the type having a fetch register arranged to receive a word from the memory, a store register adapted to receive a memory word to be restored in the memory or a new word to be stored or a word made up of bytes of a memory word to be restored and new bytes to be storeD; means responsive to the contents of said store register for generating an error correction code to be stored with the word in the store register, and means responsive to the contents of said fetch register for producing syndromes and means responsive to said syndromes for correcting an error in a word read from the memory and any corresponding error in the word or byte of a word to be restored in the memory, wherein the improvement comprises;
Claim 3
Dependent Claim
67 words
The memory of claim 1 including a store update register means responsive to said error locator circuit for transferring data to be stored into said store update register and correcting any errors in said data; means controlling said code update means to update the code in said store update register; and means controlling said store update register to provide a word to be stored in the memory.
Claim 4
Dependent Claim
54 words
The memory of claim 2 wherein said store register and said code generating means provide true and complement forms and; said means controlling said code update means comprise gates for selectively transferring from said store register to said store update register the true or complement values for correcting data errors and updating the code.
Claim 5
Dependent Claim
43 words
A memory according to claim 1 in which said code update means includes logic means differently responsive to syndrome patterns signifying data errors and to syndrome patterns signifying code errors for updating the error correction code only in response to a data error.
Claim 6
Dependent Claim
61 words
A memory according to claim 1 including a mark register identifying bytes of a memory word to be restored and bytes not to be restored wherein said code update means includes: means responsive to the output of said mark register to update the code only when a detected error occurs in a byte that is to be restored in the memory.
Claim 7
Dependent Claim
51 words
A memory according to claim 1 in which the code includes bits locating a single error and one bit detecting but not locating a double error wherein said code update means includes: means responsive to said double error detection bit to update the code only on occurrence of a single error.
Claim 8
Dependent Claim
32 words
A memory according to claim 6 in which said code update means includes: means for updating said double error detection bit according to an Extensive OR function of said other code bits.
Claim 9
Dependent Claim
64 words
A memory according to claim 1 including a mark register identifying bytes to be restored and bytes to be not restored wherein said code update means includes: means responsive to said mark register and to selected syndrome patterns signifying single data errors in bytes to be restored for updating said code only when an error has been corrected in a byte to be restored.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-01 | 1974-08-31 | 1975-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-01 | 1978-08-31 | 1979-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-01 | 1982-08-31 | 1983-03-02 | $7700.00 | Window Closed / Lapsed |