Integrated diagnostic tool

Claim 2

In a data processing system which includes an externally controllable adapter unit comprising means connected to other parts of the system for providing test initialization data thereto while the main system clocks are in a disabled condition; improved means for system diagnosis comprising: means for enabling said main system clocks, thereby putting said system into a state in which it can be utilized to perform a diagnostic test utilizing said test initialization data; completion means for sensing the completion of said diagnostic test and producing a first signal to indicate that said diagnostic test has been concluded; timing means, operative when said main system clocks are enabled, for producing a second signal if said system clocks remain enabled for a predetermined period of time; and means responsive to said first signal or said second signal for disabling said main system clocks, thereby putting said system into a state in which the results of said diagnostic test may be analyzed through said adapter unit.

Claim 3

The improved means for system diagnosis of claim 1 wherein said timing means comprises: a counter which includes overflow signalling means; and means connecting said counter to said main system clocks for causing said counter to be incremented in response to clock signals; said overflow signalling means, upon an arithmetic overflow of said counter, producing said second signal.

Claim 4

In a data processing system including system controls; said controls including a storage matrix for producing microinstruction control signals, an output register coupled to said matrix for holding a microinstruction signal for controlling system gates for one cycle of system operation, an address register coupled to said output register and to other elements of said system for selecting successive microinstruction signals from random positions in said matrix, and a source of clock pulses for defining the cycles of operation of said system; an improved test adapter for connecting external test means to said system for testing said system, said adapter comprising: transfer means responsive to signals from said external test means to transfer test initialization signals to said output register; blocking means operative concurrently with said transfer means for blocking said source of clock impulses thereby disabling said system and for blocking the coupling between said matrix and said output register; means operative subsequent to said transfer of test initialization signals to deactivate said blocking means, thereby enabling said source of clock pulses and restoring the coupling between said matrix and said output register; thereby putting said system into a state in which it can be utilized to execute a sequence of microinstructions the first of which is determined by said test initialization signals and the second of which is located in said matrix at an address defined at least in part by said test initialization signals; completion detecting means responsive to the presence in said output register of a microinstruction of a predetermined format for producing a first signal to indicate that said sequence has been concluded; timing means, operative when said blocking means is deactivated, for producing a second signal after the expiration of a predetermined time period following the start of said sequence if said blocking means remains deactivated throughout said time period; and means responsive to either said first signal or said second signal to activate said blocking means, thereby disabling said system and putting it into a state in which the results of execution of said sequence may be analyzed.

Claim 5

In a data processing system including system controls; said controls including a storage matrix for producing microinstruction control signals, an output register coupled to said matrix for holding a microinstruction signal for controlling system gates for one cycle of system operation, an address register coupled to said output register and to other elements of said system for selecting successive microinstruction signals from random positions in said matrix, and a source of clock pulses for defining the cycles of operation of said system; an improved test adapter for connecting external test means to said system for testing said system, said adapter comprising: transfer means responsive to signals from said external test means to transfer test initialization signals to said output register; blocking means operative concurrently with said transfer means for blocking said source of clock impulses thereby disabling said system and for blocking the coupling between said matrix and said output register; means operative subsequent to said transfer of test initialization signals to deactivate said blocking means, thereby enabling said source of clock pulses and restoring the coupling between said matrix and said output register; thereby putting said system into a state in which it can be utilized to execute a sequence of microinstructions the first of which is determined by said test initialization signals and the second of which is located in said matrix at an address defined at least in part by said test initialization signals; completion detecting means responsive to the presence in said output register of a microinstruction of a predetermined format for producing a first signal to indicate that said sequence has been concluded; timing means, operative when said blocking means is deactivated, for producing a second signal after the expiration of a predetermined time period following the start of said sequence if said blocking means remains deactivated throughout said time period; and means responsive to either said first signal or said second signal to activate said blocking means, thereby disabling said system and putting it into a state in which the results of execution of said sequence may be analyzed.

Claim 6

The improved test adapter of claim 3 wherein said timing means comprises: a counter; connecting means connecting said source of clock impulses to said counter for causing said counter to count clOck impulses; and time sensing means connected to said counter for causing said second signal to be produced after a predetermined number of clock impulses have been counter by said counter.

Claim 7

The improved test adapter of claim 4 further comprising: means for initializing said counter with a predetermined initial count prior to execution of said sequence; means for causing said counter to be incremented in response to clock impulses received via said connecting means; and overflow means within said counter for indicating a counter overflow condition; said overflow means being connected to said time sensing means for causing said second signal to be produced.

Claim 8

The improved test adapter of claim 4 further comprising: means for initializing said counter with a predetermined initial count prior to execution of said sequence; means for causing said counter to be decremented in response to clock impulses received via said connecting means; and underflow means within said counter for indicating a counter underflow condition; said underflow means being connected to said time sensing means for causing said second signal to be produced.

Claim 9

In a data processing system including system controls; said controls including sequence means for producing instruction control signals, an output means coupled to said sequence means for holding an instruction control signal for controlling system gates for one cycle of system operation, means for selecting successive instruction control signals from said sequence means, and a source of clock impulses for defining the cycles of operation of said system; an improved test adapter for connecting external test means to said system for testing said system, said adapter comprising: transfer means responsive to signals from said external test means to transfer test initialization signals to said system controls; blocking means operative concurrently with said transfer means for blocking said source of clock impulses thereby disabling said system; means operative subsequent to said transfer of test initialization signals to deactivate said blocking means, thereby enabling said source of clock pulses and putting said system into a state in which it can be utilized to execute a sequence of instruction control signals which starts at an address in said sequence means determined by said test initialization signals; completion detecting means responsive to the presence in said output means of an instruction control signal of a predetermined format for producing a first signal to indicate that said sequence has been concluded; timing means, operative when said blocking means is deactivated, for producing a second signal after the expiration of a predetermined time period following the start of said sequence if said blocking means remains deactivated throughout said time period; and means responsive to either said first signal or said second signal to activate said blocking means, thereby disabling said system and putting it into a state in which the results of execution of said sequence may be analyzed.

Claim 10

In a data processing system including system controls; said controls including sequence means for producing instruction control signals, an output means coupled to said sequence means for holding an instruction control signal for controlling system gates for one cycle of system operation, means for selecting successive instruction control signals from said sequence means, and a source of clock impulses for defining the cycles of operation of said system; an improved test adapter for connecting external test means to said system for testing said system, said adapter comprising: transfer means responsive to signals from said external test means to transfer test initialization signals to said system controls; blocking means operative concurrently with said transfer means for blocking said source of clock impulses thereby disabling said system; means operative subsequent to said transfer of test initialization signals to deactivate said blocking means, thereby enabling said source of clock pulses and putting said system into a state in which it can be utilized to execute a sequence of instruction control signals which starts at an address in said sequence means determined by said test initialization signals; completion detecting means responsive to the presence in said output means of an instruction control signal of a predetermined format for producing a first signal to indicate that said sequence has been concluded; timing means, operative when said blocking means is deactivated, for producing a second signal after the expiration of a predetermined time period following the start of said sequence if said blocking means remains deactivated throughout said time period; and means responsive to either said first signal or said second signal to activate said blocking means, thereby disabling said system and putting it into a state in which the results of execution of said sequence may be analyzed.

Claim 11

The improved test adapter of claim 7 wherein said timing means comprises: a counter; connecting means connecting said source of clock impulses to said counter for causing said counter to count clock impulses; and time sensing means connected to said counter for causing said second signal to be produced after a predetermined number of clock impulses have been counted by said counter.