Universal system service adapter

Claim 2

In a data processing system an adapter unit attachment to the system which is dedicated primarily to input/output of signals between system components and external equipment for system maintenance purposes comprising: means for receiving signals from said external equipment, said signals including intermixed command signals and test-related signals; and means coupled to said receiving means and responsive directly to said intermixed command signals to control said adapter unit to perform selective test operations relative to said system said operations including transferral of said test-related signals without intervening storage in system program storage from said receiving means to a select set of components in the control section of said system.

Claim 3

In the adapter of claim 1 a terminal for external signal transmission; means for collecting status signals from a multiplicity of components of said system; and means cooperative with said test operation performing means in response to particular said command signals received by said receiving means to transmit a series of signals corresponding to said status signals from said status signal collecting means to said terminal.

Claim 4

In the adapter of claim 2: means for disabling said test operation control means; and means controlled by the internal sequence controls of said system to initiate operations of said collecting means to accomplish external transmission of said status signals from said system.

Claim 5

In combination with the adapter of claim 1: main program storage means of said system; and means cooperative with said receiving means during normal operations of said system to request signal transfers intermittently from said receiving means to said main storage means whereby in effect the adapter forms an externally controlled supplemental input/output channel between external signal sources and the system.

Claim 6

In a data processing system including cyclic control means for controlling elemental clocking and gating functions of the system, said control means having enabled and disabled states of operation, a universal diagnostic test adapter comprising: first and second registers; an external signal source; means for coupling said external signal source to said first register; first means responsive to a predetermined first signal in said first register to transfer the content of said first register to said second register; second means responsive to the presence of one of a plurality of predetermined second signals in said first register to perform a test operation upon said system control means, while said control means is otherwise in said disabled state of operation, said second means being effective to transfer signals from said second register to said control means, whereby an initial test state of operation is established in said control means, and to compare status signals emanating from said control means with pass/fail reference signals supplied to one of said registers from said external source.

Claim 7

In a data processing system including cyclic control means for controlling elemental clocking and gating functions of the system, said control means having enabled and disabled states of operation, a universal diagnostic test adapter comprising: first and second registers; an external signal source; means for coupling said external signal source to said first register; first means responsive to a predetermined first signal in said first register to transfer the content of said first register to said second register; second means responsive to the presence of one of a plurality of predetermined second signals in said first register to perform a test operation upon said system control means, while said control means is otherwise in said disabled state of operation, said second means being effective to transfer signals from said second register to said control means, whereby an initial test state of operation is established in said control means, and to compare status signals emanating from said control means with pass/fail reference signals supplied to one of said registers from said external source.

Claim 8

The adapter of claim 5 in a syStem including manual control elements on an exterior system panel and associated internal circuits for controlling single cycle operations of the system, wherein said second means includes: means for emitting a discrete impulse in response to the presence of a particular said second predetermined signal in said first register; and means for transferring said impulse to said single cycle control circuits to induce a single cycle operation of said system simulating an operation of said manual control elements.

Claim 9

The adapter of claim 5 wherein said second means includes: means for conditioning the said control means from its said disabled to enable state of operation while preventing changes in the cyclic state of the control means; and means responsive to a particular second predetermined signal in said first register to operate said means for conditioning for a limited period terminating with the appearance of a third predetermined external signal in said first register.

Claim 10

The adapter of claim 5 wherein said second means includes: means responsive to the presence of a particular one of said predetermined second signals in said first register to compare an external pass/fail reference signal concurrently present in said first register to a signal emanating from and representing the instantaneous state of said system control means; and means responsive to a mismatch output of said means to compare to disable said adapter unit, whereby the state of said system when the mismatch occurred may be preserved for further examination.

Claim 11

In a data processing system including cyclic control means having enabled and disabled states of operation, a universal test adapter for coupling external devices to said control means, while the latter is in said disabled state of operations, said adapter comprising: first and second registers; means for receiving signals from sources external to said system; means for coupling said received external signals to said first register; means responsive to the presence of external signals of a first kind in said first register to transfer signals from said first register to said second register; and means responsive to the presence of external signals of a second kind in said first register to initiate selective control operations, in respect to either said adapter, said system or a said source of said external signals, in accordance with a portion of said signals of a second kind in said first register.

Claim 12

In a data processing system including cyclic control means having enabled and disabled states of operation, a universal test adapter for coupling external devices to said control means, while the latter is in said disabled state of operations, said adapter comprising: first and second registers; means for receiving signals from sources external to said system; means for coupling said received external signals to said first register; means responsive to the presence of external signals of a first kind in said first register to transfer signals from said first register to said second register; and means responsive to the presence of external signals of a second kind in said first register to initiate selective control operations, in respect to either said adapter, said system or a said source of said external signals, in accordance with a portion of said signals of a second kind in said first register.

Claim 13

The adapter as defined in claim 9 wherein said system control means includes a read-only control store ROS having a buffer control storage register for receiving control microinstruction outputs of the store and a buffer address register connected to said output register for receiving address representations designating locations of next to be selected control microinstructions in said store, said adapter including: means for transferring signals selectively from said second register of said adapter to all stages of said buffer control storage register; and means included in said means responsive to signals of said second kind for initiating subsequent to a said transfer to said control storage register an ''''ENTER ROS'''' mode of operation transferring said system control means from the disabled state to the enabled state.

Claim 14

An adapter according to claim 9 wherein said means responsive to external signals of a second kind in said first register includes: means for selectively monitoring the instantaneous states of operation of byte groups of system elements, including, but not restricted to, elements of said system control means; means coupled to said monitoring means and responsive to a particular signal of said second kind in said first register to control said monitoring means to select a byte group of system element states for monitoring; and means responsive to the same particular signal of said second kind in said first register To compare said selected byte group of system element states to respective signals in said second register representing a reference byte group.

Claim 15

An adapter according to claim 9 wherein said means responsive to predetermined external signals of said second kind in said first register includes: a manual rate switch; and means responsive to a particular signal of said second kind and the condition of operation of said manual switch to initiate repetition of an earlier transmission of signals from an external source to said first register, whereby a sequence of test operations upon said system may be cyclically repeated.

Claim 16

An adapter according to claim 9 wherein said means responsive to said signals of a second kind in said first register includes: means for forcing an error condition in a remote input-output element of said system in response to the presence of a predetermined signal of said second kind in said first register.

Claim 17

In a data processing system of circuit components arranged in LSI packages, and including an operator''s console unit with associated integrated circuit packages and panel structures devoted to manual control and indication functions of the system, a status handling subsystem to control collection of status signals from system components in said console unit, for purposes of: monitoring status log information at said panel, staging status log information for distribution to external equipment and preserving status information for reapplication to said system, comprising: a status signal line; a converging network of connecting circuits connecting multiple circuit elements of said system to said line, portions of said network being spatially integrated in the LSI packages containing respective said system circuit elements; a network of decoding-selecting gates coupled to and spatially integrated in unit packages with said network of connecting circuits; receiving circuits in said operator''s console unit; means connecting said line to said receiving circuits in said console unit; control circuits in said console unit; a plurality of control conductors connecting said control circuits in said console unit to said network of decoding-selecting gates in said system; and means in said console unit for operating said control circuits to transfer a series of encoded selection control signals to said plurality of control conductors to establish thereby paths for selective bit-serial transmission of binary state signals through said network of connecting gates between a corresponding series of binary components of said system and said receiving circuits in said console unit.

Claim 18

In a data processing system of circuit components arranged in LSI packages, and including an operator''s console unit with associated integrated circuit packages and panel structures devoted to manual control and indication functions of the system, a status handling subsystem to control collection of status signals from system components in said console unit, for purposes of: monitoring status log information at said panel, staging status log information for distribution to external equipment and preserving status information for reapplication to said system, comprising: a status signal line; a converging network of connecting circuits connecting multiple circuit elements of said system to said line, portions of said network being spatially integrated in the LSI packages containing respective said system circuit elements; a network of decoding-selecting gates coupled to and spatially integrated in unit packages with said network of connecting circuits; receiving circuits in said operator''s console unit; means connecting said line to said receiving circuits in said console unit; control circuits in said console unit; a plurality of control conductors connecting said control circuits in said console unit to said network of decoding-selecting gates in said system; and means in said console unit for operating said control circuits to transfer a series of encoded selection control signals to said plurality of control conductors to establish thereby paths for selective bit-serial transmission of binary state signals through said network of connecting gates between a corresponding series of binary components of said system and said receiving circuits in said console unit.

Claim 19

The status handling subsystem of claim 14 including: a buffer store contained within said console unit, said buffer store having the capacity to store series of status signals; means in said console unit for transferring a said series of status signals, received in said receiving circuits from said series of elements, to predetermined locations of said buffer store in a predetermined sequence; and means associated with said console unit control circuits and said transfer operating means to produce and transfer an aggregate status log of said system elements to said buffer store via said receiving circuits.

Claim 20

The status handling subsystem of claim 15 including means for transferring status signals from said console buffer store selectively to indicating elements on the panel of said console unit, to equipment external to said system and to storage elements of said system.

Claim 21

In a data processing system in combination a maintenance section including status collection and test adapter subsections including: a console unit in the collection subsection including a buffer input register, a matrix buffer store coupled to the output of the input register, means for scanning system component state signals into said input register in a predetermined sequence, and A panel display coupled to the output of the buffer store; means for transferring said system component state signals directly from said console unit buffer input register and indirectly from said buffer store into said test adapter subsection; first and second buffer registers in said adapter subsection; and means in said adapter subsection and console unit responsive to a signal in said first register of said adapter and cooperative with said transferring means to transfer said system state signals in said predetermined sequence from said console unit to said second register in said adapter subsection.

Claim 22

In a data processing system in combination a maintenance section including status collection and test adapter subsections including: a console unit in the collection subsection including a buffer input register, a matrix buffer store coupled to the output of the input register, means for scanning system component state signals into said input register in a predetermined sequence, and A panel display coupled to the output of the buffer store; means for transferring said system component state signals directly from said console unit buffer input register and indirectly from said buffer store into said test adapter subsection; first and second buffer registers in said adapter subsection; and means in said adapter subsection and console unit responsive to a signal in said first register of said adapter and cooperative with said transferring means to transfer said system state signals in said predetermined sequence from said console unit to said second register in said adapter subsection.

Claim 23

A status collection and adapter combination as defined in claim 17 and including means in said adapter coordinated with the transfer means last mentioned in claim 17 to transfer said signals received in said second register to an external transmission medium in a standardized bit-serial transmission format whereby system status signals are transmitted for external collection.

Claim 24

The subsystem defined in claim 18 including means in said adapter and console unit responsive to address signals received in said first register of said adapter to select an initial state signal position in said predetermined scanning sequence as a starting position for said transfer to said second register.

Claim 25

The subsystem of claim 18 wherein said adapter includes: means coordinated with the means to transfer signals from the second register to the said external transmission medium, for calculating and transmitting new check signals to supplement respective groups of signals transmitted from the second register; a third register; means coupled to said console unit to receive and transfer earlier calculated check signal information from said console unit to selected sections of said third register, and means coordinated with the said means transferring said state signals to said second register, to intermittently transfer groups of said earlier-calculated check signals from said third register to said second register to effectively cause alternate and discretely separate transmission of groups of state and earlier supplemental check each group containing respective new check signals to supplement the group.

Claim 26

In a data processing system including system controls-said controls including a read-only store matrix for producing microinstruction control signals, an output buffer register coupled to said matrix for holding a microinstruction signal for controlling system gates for one discrete cycle of system operation, an address buffer register coupled to said output buffer register and other elements of said system for selecting successive microinstruction signals from random positions in said matrix, and a source of clock impulses for defining the discrete cycles of operation of the said system-a test adapter for connecting external test equipment to said system for testing said system, said adapter comprising: first and second registers; means for coupling signals from said external test equipment to said first register; means responsive to signals in said first register to transfer signals from said first register to said second register; means responsive to signals in said first register to transfer signals from said second register to said output buffer register of said read-only store matrix of said system; means operative concurrently with said last-mentioned means in response to signals in said first register to initiate a discrete cycle of operation of said system while said source of clock impulses is blocked and disabling said system and while the coupling between said read-only store matrix and said output buffer register thereof is also held blocked; means operative concurrently with said last-mentioned means for comparing a signal entered into said address buffer register with a signal stored in said first register; and means responsive to a mismatch output of said comparing means to prevent further operation of said cycle initiating means.

Claim 27

In a data processing system including system controls-said controls including a read-only store matrix for producing microinstruction control signals, an output buffer register coupled to said matrix for holding a microinstruction signal for controlling system gates for one discrete cycle of system operation, an address buffer register coupled to said output buffer register and other elements of said system for selecting successive microinstruction signals from random positions in said matrix, and a source of clock impulses for defining the discrete cycles of operation of the said system-a test adapter for connecting external test equipment to said system for testing said system, said adapter comprising: first and second registers; means for coupling signals from said external test equipment to said first register; means responsive to signals in said first register to transfer signals from said first register to said second register; means responsive to signals in said first register to transfer signals from said second register to said output buffer register of said read-only store matrix of said system; means operative concurrently with said last-mentioned means in response to signals in said first register to initiate a discrete cycle of operation of said system while said source of clock impulses is blocked and disabling said system and while the coupling between said read-only store matrix and said output buffer register thereof is also held blocked; means operative concurrently with said last-mentioned means for comparing a signal entered into said address buffer register with a signal stored in said first register; and means responsive to a mismatch output of said comparing means to prevent further operation of said cycle initiating means.

Claim 28

An adapter, as defined in claim 21, in combination with: third and fourth registers; means responsive to signals in said first register to transfer concurrently status signals from said data processing system to said third register and check signals from said data processing system to said fourth register; and means coordinated with said last-mentioned means to alternately transmit to said external equipment plural groups of said status signals received in said third register and single groups of associated check signals.

Claim 29

An adapter as defined in claim 21 in combination with: means for selectively monitoring status signals within said system in byte groups in accordance with byte selection information received in said first register; and means coupled to said monitor means and responsive to control signals in said first register to compare said selected status signal groups to signals stored in said second register of said adapter unit.

Claim 30

An adapter as defined in claim 21 in which said read-only store matrix output buffer is subdivided into a plurality of sections; said second register of said adapter unit is subdivided into a plurality of subsections; and said means for transferring signals from said first register to said second register in said adapter unit is effective to selectively transfer said signals to said subsections of said second register.

Claim 31

An adapter as in claim 24: wherein said means for transferring signals from said second register to said output buffer register of said matrix includes gating means spatially integrated with the circuits of said buffer register and matrix for selectively transferring said second register signals to sections of said output buffer register.

Claim 32

An adapter as defined in claim 25 wherein: said means for transferring between said first register and second register of the adapter and between said second register of the adapter and output buffer register of the read-only store matrix are adapted to modify a selected portion or the whole of the contents of the output buffer store of the read-only store data matrix prior to initiation of a said cycle of operation of said system.

Claim 33

In a data processing system an externally controllable test adapter section to carry test-related binary signals bidirectionally between elements of said data processing system and equipment external to said system for the purpose of remotely testing said system in response to signals sent from said equipment, said adapter section having input signal connections only to a select nucleus of components in the control section of said system for relaying test signals from said equipment to said components under control of said equipment, said adapter section having output connections to components of said system including but not restricted to said nucleus for collecting state signals from said components and for incorporating such signals in transmissions to said external equipment.

Claim 34

In a data processing system an externally controllable test adapter section to carry test-related binary signals bidirectionally between elements of said data processing system and equipment external to said system for the purpose of remotely testing said system in response to signals sent from said equipment, said adapter section having input signal connections only to a select nucleus of components in the control section of said system for relaying test signals from said equipment to said components under control of said equipment, said adapter section having output connections to components of said system including but not restricted to said nucleus for collecting state signals from said components and for incorporating such signals in transmissions to said external equipment.

Claim 35

As an auxiliary physical appendage and electrically connected service feature of a data processing system an externally controllable adaptive signal converter unit comprising: a buffer register; means for connecting outputs of said register with select groups of internal elements of said system; a signal receiver for receiving coded signals, including distinctively coded unit command signals and system stimuli signals, from external equipment physically removed from said unit and system; means responsive to the codes of said received stimuli signals to selectively transfer said stimuli signals into said buffer register; and means responsive to certain of said unit command signals to operate said output connecting means to transfer said stimuli signals from said buffer register to said internal system elements without assistance from the system.

Claim 36

As an auxiliary physical appendage and electrically connected service feature of a data processing system an externally controllable adaptive signal converter unit comprising: a buffer register; means for connecting outputs of said register with select groups of internal elements of said system; a signal receiver for receiving coded signals, including distinctively coded unit command signals and system stimuli signals, from external equipment physically removed from said unit and system; means responsive to the codes of said received stimuli signals to selectively transfer said stimuli signals into said buffer register; and means responsive to certain of said unit command signals to operate said output connecting means to transfer said stimuli signals from said buffer register to said internal system elements without assistance from the system.

Claim 37

In combination with a data processing sysTem an externally controllable test adapter unit incorporated in the system as a common service feature of the system comprising: means for receiving intermixed test stimuli signals and coded command signals from equipment physically removed from said system; and means responsive to said command signals for controlling testing of said system by coupling said stimuli signals to select control components of said system to stimulate said components to produce artificial test states in said system.

Claim 38

In combination with a data processing sysTem an externally controllable test adapter unit incorporated in the system as a common service feature of the system comprising: means for receiving intermixed test stimuli signals and coded command signals from equipment physically removed from said system; and means responsive to said command signals for controlling testing of said system by coupling said stimuli signals to select control components of said system to stimulate said components to produce artificial test states in said system.

Claim 39

An adapter unit according to claim 29 wherein said means for controlling testing includes means responsive to particular said command signals for collecting test response signals from said system.

Claim 40

An adapter unit according to claim 30 wherein said means for controlling testing includes means for transmitting said collected test response signals to a said removed equipment for evaluation.

Claim 41

An adapter unit according to claim 31 including input and output timing circuit sections for controlling the operations of said respective receiving and transmitting means.