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US3814917A
Expired / Lapsed
US
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Signal processing device for weighting delta coded sequences by pair wise summation of coefficients according to the matching condition of counterpart delta digits
Assignee: International Business Machines Corp
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Filing: 1973-05-29
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Granted: 1974-06-04
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Expires: 1993-05-29
Abstract
Abstract An input analog signal is sampled and then DELTA coded. The resulting DELTA bits x(t-+96{l ), x(t-2 tau ), x(t-3 tau )- x(t-2N tau ) are recirculated through a shift register at a frequency N times higher than the sampling frequency. The high cycling rate makes it possible to automatically multiplex the coefficient weighting of the DELTA coded bits coming from the shift register. The multiplexing operation is carried out in such a manner such that at each shift instant, two DELTA bits are available in parallel. The weighting coefficients C1, C2, C3 - C2N are processed pair wise in the form of sums and differences (+/-C1+/-C2); (+/-C3+/-C4) of the coefficients, the sum or difference being formed according as to whether the counterpart pair of DELTA bits matched or mismatched (00, 01, 10, 11) i.e., x(t- tau ) > x(t-2 tau ), x(t- tau ) < x(t-2 tau ) or x(t- tau ) = x(t-2 tau ) = [01. The relative values of two DELTA coded bits coming from the shift register at a given instant control the selection of binary characters available in the parallel form and being representative either of the sum of the cwo corresponding coefficients or the different thereof, or the value opposite to the sum or the value opposite to the difference. These binary characters are successively accumulated in the accumulator, the output of which supplies a differential PCM-coded sample of the filtered signal, upon each period of the sampling frequency.
Inventors
- 👤 H Nussbaumer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:00
CPC Classifications
H; H04; H04B; H04B14/00; H04B14/02; H04B14/06; H04B14/062; H04B14/064
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
178 words
A process for carrying out the sum of two sequences of delta bits weighted with binary coefficients, one coefficient being assigned to each delta bit, wherein the process includes the following steps: carrying out the sums and differences of the coefficients corresponding to the delta bits of the same rank in both sequences, in the parallel form, comparing the values of the two delta bits of the same rank in both sequences, fetching either the character representative of the sum of the corresponding coefficients, should the combination of the two bits be 11 or 00, or the character representative of the difference of the coefficients, should the combination be 01 or 10, applying the binary character obtained at the preceding step, should the corresponding combination be 11 or 01, or the binary character representative of the value opposite to that represented by the charactEr obtained at the preceding step, should the corresponding combination be 10 or 00, at the inputs of an accumulator, accumulating the so-presented binary characters for each bit rank in the two delta bit sequences.
Claim 2
Dependent Claim
178 words
A process for carrying out the sum of two sequences of delta bits weighted with binary coefficients, one coefficient being assigned to each delta bit, wherein the process includes the following steps: carrying out the sums and differences of the coefficients corresponding to the delta bits of the same rank in both sequences, in the parallel form, comparing the values of the two delta bits of the same rank in both sequences, fetching either the character representative of the sum of the corresponding coefficients, should the combination of the two bits be 11 or 00, or the character representative of the difference of the coefficients, should the combination be 01 or 10, applying the binary character obtained at the preceding step, should the corresponding combination be 11 or 01, or the binary character representative of the value opposite to that represented by the charactEr obtained at the preceding step, should the corresponding combination be 10 or 00, at the inputs of an accumulator, accumulating the so-presented binary characters for each bit rank in the two delta bit sequences.
Claim 3
Independent Claim
250 words
A device for carrying out the sum of the weightings of two delta bit sequences, respectively, by binary digital coefficients available in the parallel form, each delta bit of each sequence being assigned a weighting coefficient, the device includes: logic summation means for summing the coefficients corresponding to the two bits of the same row in the two sequences in order to generate the sums and differences of said coefficients considered two by two, comparison means receiving the delta bits of the same rank in both delta bit sequences to compare the values of these two bits and indicate whether they are equal or different, selection means receiving the sum and difference of the two corresponding coefficients to select the sum or difference according as the comparison means are indicative of an equality or a difference, detection means receiving one of the two delta bits to detect its binary value, selection inversion means operating in response to the detection of a first binary value by the detection means in order to generate the binary character representative of the value opposite to the value represented by the sum or difference selected by the selection means, and to the detection of the second binary value by the detection means in order to pass, without any modification, the binary character representative of the sum or difference selected by the selection means, and accumulation means for accumulating the successive character coming from the selective inversion means as the two delta bit sequences are processed.
Claim 4
Independent Claim
250 words
A device for carrying out the sum of the weightings of two delta bit sequences, respectively, by binary digital coefficients available in the parallel form, each delta bit of each sequence being assigned a weighting coefficient, the device includes: logic summation means for summing the coefficients corresponding to the two bits of the same row in the two sequences in order to generate the sums and differences of said coefficients considered two by two, comparison means receiving the delta bits of the same rank in both delta bit sequences to compare the values of these two bits and indicate whether they are equal or different, selection means receiving the sum and difference of the two corresponding coefficients to select the sum or difference according as the comparison means are indicative of an equality or a difference, detection means receiving one of the two delta bits to detect its binary value, selection inversion means operating in response to the detection of a first binary value by the detection means in order to generate the binary character representative of the value opposite to the value represented by the sum or difference selected by the selection means, and to the detection of the second binary value by the detection means in order to pass, without any modification, the binary character representative of the sum or difference selected by the selection means, and accumulation means for accumulating the successive character coming from the selective inversion means as the two delta bit sequences are processed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-03 | 1977-12-03 | 1978-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-03 | 1981-12-03 | 1982-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-03 | 1985-12-03 | 1986-06-04 | $7700.00 | Window Closed / Lapsed |