Digital filter and threshold circuit

Claim 2

In a filter of the transversal type in which a series of pulses is applied through a delay element, such as an n stage shift register in which a preselected m of the n stages is assigned a corresponding arithmetic weighting ai, the combination comprising: means for counting in base b to an upper limit of br; and a logic arrangement for distributing the signal present at preselected ones of the shift register stages to those counter stages the sum of whose count capacity for each selected ai where q r.

Claim 3

A digital filter comprising: an n shift stage register in which a preselected m of the n stages is assigned a corresponding arithmetic weighting ai; means for applying a pulse train to the shift register; a counter in base b having an upper limit of br; and a logic arrangement for distributing the signal present at preselected ones of the m of n shift register stages only to those counter stages the sum of whose count capacity for each selected ai where q is less than or equal to r.

Claim 4

A digital filter comprising: an n shift stage register in which a preselected m of the n stages is assigned a corresponding arithmetic weighting ai; means for applying a pulse train to the shift register; a counter in base b having an upper limit of br; and a logic arrangement for distributing the signal present at preselected ones of the m of n shift register stages only to those counter stages the sum of whose count capacity for each selected ai where q is less than or equal to r.

Claim 5

In a filter of the transversal type in which a series of binary pulses are cyclically applied to an n stage shift register and, further, in which each of m preselected stages is assigned a corresponding arithmetic weight ai, the combination comprising: a binary counter having r stages; a logic arrangement for distributing the signal present at preselected ones of the m shift register stages only to those counter stages the sum of whose count capacity for each selected ai, where q is less than or equal to r; and means coupled to the binary counter for providing signal indication if the binary signal counter magnitude is greater than a reference value.

Claim 6

In a filter of the transversal type in which a series of binary pulses are cyclically applied to an n stage shift register and, further, in which each of m preselected stages is assigned a corresponding arithmetic weight ai, the combination comprising: a binary counter having r stages; a logic arrangement for distributing the signal present at preselected ones of the m shift register stages only to those counter stages the sum of whose count capacity for each selected ai, where q is less than or equal to r; and means coupled to the binary counter for providing signal indication if the binary signal counter magnitude is greater than a reference value.

Claim 7

In a data-transmission system in which only fluctuations in signal amplitude from sampling instant to sampling instant are encoded in binary and further wherein each binary signal represents the fact that the corresponding signal magnitude exceeds the sum of the prior differences between the instant magnitude and a reference, said system comprising: an n-stage shift register; means for applying successive binary signals to the shift register; a binary counter; a logic arrangement for distributing the binary signals present at a preselected m of the n shift register stages to preselected ones of the counter stages; and means coupled to the binary counter means for providing signal indication if the binary counter signal magnitude is greater than a reference value.

Claim 8

In a data-transmission system in which only fluctuations in signal amplitude from sampling instant to sampling instant are encoded in binary and further wherein each binary signal represents the fact that the corresponding signal magnitude exceeds the sum of the prior differences between the instant magnitude and a reference, said system comprising: an n-stage shift register; means for applying successive binary signals to the shift register; a binary counter; a logic arrangement for distributing the binary signals present at a preselected m of the n shift register stages to preselected ones of the counter stages; and means coupled to the binary counter means for providing signal indication if the binary counter signal magnitude is greater than a reference value.

Claim 9

A digital filter according to claim 2, wherein the logic arrangement includes: a source of selection signals; m OR gates coupling corresponding ones of m counter stages where m is less than or equal to r; m AND gates terminating corresponding ones of the m shift register stages as a first input, each AND gate coupling only those counter stages through the associate OR gate, the sum of whose count capacity for each ai, where q is less than or equal to r; and means for activating only those AND gates corresponding to the selection signal source.

Claim 10

In a data-transmission system including a transmission medium having a nonlinear attenuation versus phase characteristic; means For impressing an analog signal upon the medium; and a receiver coupling said medium; the combination comprising: means at the receiver responsive to the analog signal for providing a delta modulated equivalence represented by a binary pulse train; an n-stage shift register; means for applying the binary pulse train to the shift register; a binary counter; a logic arrangement responsive to separately coded indicia for distributing the binary pulses present at a preselected m of the n shift register stages to preselected ones of the counter stages; and means coupled to the binary counter for providing signal indication if the binary counter signal magnitude is greater than a reference value, whereby alteration of the logic arrangement by varying the coded indicia effectively provides a linearizing phase characteristic.

Claim 11

In a data-transmission system including a transmission medium having a nonlinear attenuation versus phase characteristic; means For impressing an analog signal upon the medium; and a receiver coupling said medium; the combination comprising: means at the receiver responsive to the analog signal for providing a delta modulated equivalence represented by a binary pulse train; an n-stage shift register; means for applying the binary pulse train to the shift register; a binary counter; a logic arrangement responsive to separately coded indicia for distributing the binary pulses present at a preselected m of the n shift register stages to preselected ones of the counter stages; and means coupled to the binary counter for providing signal indication if the binary counter signal magnitude is greater than a reference value, whereby alteration of the logic arrangement by varying the coded indicia effectively provides a linearizing phase characteristic.

Claim 12

In a data-transmission system in which only fluctuations in signal amplitude from sampling instant to sampling instant are encoded in binary and further wherein each binary signal represents the fact that the corresponding signal magnitude exceeds the sum of the prior differences between the instant magnitude and a reference; said system comprising: an N-stage shift register; means for applying successive binary signals to the shift register; a weighting circuit having M-input ports; and a logic arrangement responsive to separately coded indicia for distributing the binary signals present at a preselected M of the N shift register stages to preselected and corresponding ones of the M-input ports.

Claim 13

In a data-transmission system in which only fluctuations in signal amplitude from sampling instant to sampling instant are encoded in binary and further wherein each binary signal represents the fact that the corresponding signal magnitude exceeds the sum of the prior differences between the instant magnitude and a reference; said system comprising: an N-stage shift register; means for applying successive binary signals to the shift register; a weighting circuit having M-input ports; and a logic arrangement responsive to separately coded indicia for distributing the binary signals present at a preselected M of the N shift register stages to preselected and corresponding ones of the M-input ports.