US3801964A
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US
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Semiconductor memory with address decoding
Assignee: Advanced Memory Systems Inc
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Filing: 1972-02-24
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Granted: 1974-04-02
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Expires: 1992-02-24
Abstract
Abstract A dynamic semiconductor memory, including a memory addressing system, using field effect devices, for rapidly decoding an address signal, for addressing the memory matrix, and providing a differential output on a pair of sense lines in accordance with the state of the addressed memory cell. The system is comprised of three basic addressing circuits operating in conjunction with a reset signal and clock signal to address one of the memory cells in the memory. The first circuit generates a reset signal which is the modified inverse of the reset signal for use in the second circuit. The second circuit is an address inverter, used in plurality, each of which presents one bit of the multiple bit address together with an inverse thereof, and serves as a register for the signal for application to the decoder circuit. The third circuit is a decoder circuit, used for each row and each column of the memory matrix, which receives the address and/or address signal and provides a clocked, decoded address signal output. The decoded row address couples each memory cell in the respective row to a pair of precharged column cell lines, and the decoded column address couples one respective pair of the column cell lines to the sense lines, whereby a chip select signal (the column ''''clock'''' signal) may be used to couple the sense lines to the I/O (input-output) lines. Refresh and write operations are described.
Inventors
- 👤 T Palfi
- 👤 J Oliphant
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:27
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4087; G11C11/402; G11C11/4023
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
420 words
A memory system comprising a plurality of devices of the insulated gate type whereby conduction between first and second regions in a semiconductor maybe controlled by the voltage on an insulated gate, having; a plurality of cells electrically arranged in columns and rows, each of said cells having first, second, third and fourth devices, said first and second devices having their first regions coupled to a first power supply connection and their second regions coupled to the first regions of said third and fourth devices respectively, said gates of said first and second devices being coupled to the first regions of said fourth and third devices respectively, the gates of said third and fourth devices being coupled to the row address line for the respective row of cells, said sEcond regions of said third and fourth devices each being coupled to one of a pair of column cell lines for the respective column of cells, means for precharging said column cell lines to a predetermined voltage in response to a first timing signal. means for coupling each of a selected pair of column cell lines to a respective one of a pair of sense lines responsive to a column address signal applied to respective column address lines. a plurality of address inverter means, each for receiving and inverting one bit of a multiple bit addressing signal and coupling each said bit and the inverse thereof to first and second address inverter output terminals in response to a second timing signal, reset means for resetting the voltage on each of said address inverter means output terminals to a predetermined voltage level in response to said first timing signal, a plurality of decoder means, each for receiving a signal from a predetermined one of said address inverter output terminals of each of a plurality of said address inverter means and for providing a decoded signal; and coupling means coupled to each said decoder means for receiving said decoded signal and coupling said decoded signal to a decoded output line in response to a timing signal applied thereto, said coupling means and said decoder means being functionally divided into first and second groups, the coupling means of each of said first group being responsive to a third timing signal to couple said decoded signal to a respective one of said row address lines, said coupling means of each of said second group being responsive to a fourth timing signal to couple said decoded signal to a respective one of said column address lines.
Claim 2
Dependent Claim
420 words
A memory system comprising a plurality of devices of the insulated gate type whereby conduction between first and second regions in a semiconductor maybe controlled by the voltage on an insulated gate, having; a plurality of cells electrically arranged in columns and rows, each of said cells having first, second, third and fourth devices, said first and second devices having their first regions coupled to a first power supply connection and their second regions coupled to the first regions of said third and fourth devices respectively, said gates of said first and second devices being coupled to the first regions of said fourth and third devices respectively, the gates of said third and fourth devices being coupled to the row address line for the respective row of cells, said sEcond regions of said third and fourth devices each being coupled to one of a pair of column cell lines for the respective column of cells, means for precharging said column cell lines to a predetermined voltage in response to a first timing signal. means for coupling each of a selected pair of column cell lines to a respective one of a pair of sense lines responsive to a column address signal applied to respective column address lines. a plurality of address inverter means, each for receiving and inverting one bit of a multiple bit addressing signal and coupling each said bit and the inverse thereof to first and second address inverter output terminals in response to a second timing signal, reset means for resetting the voltage on each of said address inverter means output terminals to a predetermined voltage level in response to said first timing signal, a plurality of decoder means, each for receiving a signal from a predetermined one of said address inverter output terminals of each of a plurality of said address inverter means and for providing a decoded signal; and coupling means coupled to each said decoder means for receiving said decoded signal and coupling said decoded signal to a decoded output line in response to a timing signal applied thereto, said coupling means and said decoder means being functionally divided into first and second groups, the coupling means of each of said first group being responsive to a third timing signal to couple said decoded signal to a respective one of said row address lines, said coupling means of each of said second group being responsive to a fourth timing signal to couple said decoded signal to a respective one of said column address lines.
Claim 3
Dependent Claim
55 words
The memory system of claim 1 further comprised of a means for precharging said sense lines to a predetermined voltage in response to said second timing signal and a means for coupling each of said pair of sense lines to a respective one of a pair of input-output terminals responsive to said fourth timing signal.
Claim 4
Dependent Claim
78 words
The memory system of claim 1 wherein said coupling means each comprises fifth and sixth devices, said fifth device having its first region coupled to a line to receive said timing signal, its second region coupled to said decoded output line, and its gate coupled to said second region of said sixth device, said sixth device also having its first region coupled to said decoder for receiving said decoded signal and its gate coupled to a predetermined voltage.
Claim 5
Dependent Claim
32 words
The memory system of claim 3 wherein said gate of said fifth device is disposed over a significant area of its said second region so as to substantially increase the capacitance therebetween.
Claim 6
Dependent Claim
212 words
A memory system comprising a plurality of devices of the insulated gate type whereby conduction between first and second regions in a semiconductor may be controlled by the voltage on an insulated gate having: a plurality of memory cell means electrically arranged in columns and rows, each said row and each said column having at least one row line and one column line respectively whereby one said cell may be activated by addressing the respective one said row line and one said column line, a plurality of decoder means, each for receiving a plurality of address signals and for providing a decoded output signal, and a plurality of coupling means each for coupling said decoded output signal of each said decoder to a respective one of said row lines and said column lines, each said coupling means having first and second devices, said first device having its first region coupled to a line to receive a timing signal, its second region coupled to a respective one of said row and column lines, and its gate coupled to said second region of said second device, said second device having its first region coupled to said decoder means to receive one of said decoded output signals and its gate coupled to a predetermined voltage.
Claim 7
Dependent Claim
212 words
A memory system comprising a plurality of devices of the insulated gate type whereby conduction between first and second regions in a semiconductor may be controlled by the voltage on an insulated gate having: a plurality of memory cell means electrically arranged in columns and rows, each said row and each said column having at least one row line and one column line respectively whereby one said cell may be activated by addressing the respective one said row line and one said column line, a plurality of decoder means, each for receiving a plurality of address signals and for providing a decoded output signal, and a plurality of coupling means each for coupling said decoded output signal of each said decoder to a respective one of said row lines and said column lines, each said coupling means having first and second devices, said first device having its first region coupled to a line to receive a timing signal, its second region coupled to a respective one of said row and column lines, and its gate coupled to said second region of said second device, said second device having its first region coupled to said decoder means to receive one of said decoded output signals and its gate coupled to a predetermined voltage.
Claim 8
Dependent Claim
32 words
The memory system of claim 5 wherein said gate oF said first device is disposed over a significant area of its said second region so as to substantially increase the capacitance therebetween.
Claim 9
Dependent Claim
374 words
A memory system comprising a plurality of devices of the insulated gate type whereby conduction between first and second regions in a semiconductor may be controlled by the voltage on an insulated gate, having: a plurality of cells electrically arranged in columns and rows, each of said cells having first, second, third and fourth devices, said first and second devices having their first regions coupled to a first power supply connection and their second regions coupled to the first regions of said third and fourth devices respectively, said gates of said first and second devices being coupled to the first regions of said fourth and third devices respectively, the gates of said third and fourth devices being coupled to the row address line for the respective row of cells, said second regions of said third and fourth devices each being coupled to one of a pair of column cell lines for the respective column of cells, means for coupling each of a selected pair of column cell lines to a respective one of a pair of sense lines responsive to a column address signal applied to respective column address lines, a plurality of address inverter means, each for receiving and inverting one bit of a multiple bit addressing signal and coupling each said bit and the inverse thereof to first and second address inverter output terminals in response to a first timing signal, a plurality of decoder means, each for receiving a signal from a predetermined one of said address inverter output terminals of each of a plurality of said address inverter means and for providing a decoded signal, and coupling means coupled to each said decoder means for receiving said decoded signal and coupling said decoded signal to a decoded output line in response to a timing signal applied thereto, said coupling means and said decoder means being functionally divided into first and second groups, the coupling means of each of said first group being responsive to a timing signal to couple said decoded signal to a respective one of said row address lines, said coupling means of each of said second group being responsive to a timing signal to couple said decoded signal to a respective one of said column address lines.
Claim 10
Dependent Claim
374 words
A memory system comprising a plurality of devices of the insulated gate type whereby conduction between first and second regions in a semiconductor may be controlled by the voltage on an insulated gate, having: a plurality of cells electrically arranged in columns and rows, each of said cells having first, second, third and fourth devices, said first and second devices having their first regions coupled to a first power supply connection and their second regions coupled to the first regions of said third and fourth devices respectively, said gates of said first and second devices being coupled to the first regions of said fourth and third devices respectively, the gates of said third and fourth devices being coupled to the row address line for the respective row of cells, said second regions of said third and fourth devices each being coupled to one of a pair of column cell lines for the respective column of cells, means for coupling each of a selected pair of column cell lines to a respective one of a pair of sense lines responsive to a column address signal applied to respective column address lines, a plurality of address inverter means, each for receiving and inverting one bit of a multiple bit addressing signal and coupling each said bit and the inverse thereof to first and second address inverter output terminals in response to a first timing signal, a plurality of decoder means, each for receiving a signal from a predetermined one of said address inverter output terminals of each of a plurality of said address inverter means and for providing a decoded signal, and coupling means coupled to each said decoder means for receiving said decoded signal and coupling said decoded signal to a decoded output line in response to a timing signal applied thereto, said coupling means and said decoder means being functionally divided into first and second groups, the coupling means of each of said first group being responsive to a timing signal to couple said decoded signal to a respective one of said row address lines, said coupling means of each of said second group being responsive to a timing signal to couple said decoded signal to a respective one of said column address lines.
Claim 11
Dependent Claim
78 words
The memory system of claim 7 wherein said coupling means each comprises fifth and sixth devices, said fifth device having its first region coupled to a line to receive said timing signal, its second region coupled to said decoded output line, and its gate coupled to said second region of said sixth device, said sixth device also having its first region coupled to said decoder for receiving said decoded signal and its gate coupled to a predetermined voltage.
Claim 12
Dependent Claim
32 words
The memory system of claim 8 wherein said gate of said fifth device is disposed over a significant area of its said second region so as to substantially increase the capacitance therebetween.
Claim 13
Dependent Claim
197 words
A memory system comprising a plurality of devices of the insulated gate type whereby conduction between first and second regions in a semiconductor may be controlled by the voltage on an insulated gate having: a plurality of memory cell means electrically arranged in columns and rows, each said row having at least one row line and one column line respectively whereby one said cell may be activated by addressing the respective one said row line, a plurality of decoder means, each for receiving a plurality of address signals and for providing a decoded output signal, and a plurality of coupling means each for coupling said decoded output signal of each said decoder to a respective one of said row lines, each said coupling means having first and second devices, said first device having its first region coupled to a line to receive a timing signal, its second region coupled to a respective one of said row lines, and its gate coupled to said second region of said Second device, said second device having its first region coupled to said decoder means to receive one of said decoded output signals and it gate coupled to a predetermined voltage.
Claim 14
Dependent Claim
197 words
A memory system comprising a plurality of devices of the insulated gate type whereby conduction between first and second regions in a semiconductor may be controlled by the voltage on an insulated gate having: a plurality of memory cell means electrically arranged in columns and rows, each said row having at least one row line and one column line respectively whereby one said cell may be activated by addressing the respective one said row line, a plurality of decoder means, each for receiving a plurality of address signals and for providing a decoded output signal, and a plurality of coupling means each for coupling said decoded output signal of each said decoder to a respective one of said row lines, each said coupling means having first and second devices, said first device having its first region coupled to a line to receive a timing signal, its second region coupled to a respective one of said row lines, and its gate coupled to said second region of said Second device, said second device having its first region coupled to said decoder means to receive one of said decoded output signals and it gate coupled to a predetermined voltage.
Claim 15
Dependent Claim
33 words
The memory of system of claim 10 wherein said gate of said first device is disposed over a significant area of its said second region so as to substantially increase the capacitance therebetween.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-04-01 | 1977-10-01 | 1978-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-04-01 | 1981-10-01 | 1982-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-04-01 | 1985-10-01 | 1986-04-02 | $7700.00 | Window Closed / Lapsed |