US3706975A
Expired / Lapsed
US
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High speed mos random access memory
Assignee: Texas Instruments Inc
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Filing: 1970-10-09
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Granted: 1972-12-19
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Expires: 1990-10-09
Abstract
Abstract Disclosed is a high speed insulated gate field effect transistor random access memory circuit integrated on a monolithic chip. The memory circuit utilizes a low voltage decoding circuit that is compatible with transistor-transistor-logic circuit output levels, enabling a reduction in the number of discrete MOS devices required for each memory cell. Also disclosed is a novel method for decoding wherein all of the lines of the memory matrix are brought high at the start of each cycle, recharging the internal capacitance of all of the memory cells of the matrix. All of the undesired lines of the memory matrix are then discharged through an OR circuit arrangement connected in series with each line, thereby disconnecting all but a preselected cell of the memory matrix from the computer input/output sense lines.
Inventors
- 👤 Robert J Paluck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:34
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4087; G11C11/402; G11C11/4023
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
71 words
An integrated circuit insulated gate field effect transistor random access memory system comprising in combination on a semiconductor chip: a. a matrix of memory cells; b. means for simultaneously addressing all cells with a high signal to thereby recharge the capacitance of each cell; c. means for removing said high signal from all cells except a preselected one; and d. means for connecting said preselected cell to computer input/output sense lines.
Claim 2
Dependent Claim
71 words
An integrated circuit insulated gate field effect transistor random access memory system comprising in combination on a semiconductor chip: a. a matrix of memory cells; b. means for simultaneously addressing all cells with a high signal to thereby recharge the capacitance of each cell; c. means for removing said high signal from all cells except a preselected one; and d. means for connecting said preselected cell to computer input/output sense lines.
Claim 3
Dependent Claim
48 words
A memory system as set forth in claim 1 wherein said means for removing high signals from all but a preselected cell includes a plurality of insulated gate field effect transistors formed on the chip as an OR circuit, said transistors being directly compatible with transistor-transistor-logic input levels.
Claim 4
Dependent Claim
56 words
A memory system in accordance with claim 1 wherein each of said plurality of memory cells comprises four insulated gate field effect transistors, two of which define a cross-coupled flip-flop operative to store a bit of data, and the other two of which are operative to isolate said flip-flop from other memory cells of said system.
Claim 5
Dependent Claim
160 words
In a random access memory computer system wherein the central processing unit of the computer defines x and y coordinates of a preselected cross-coupled flip-flop memory cell to be operated on by the computer and translates these coordinates to an insulated gate field effect transistor memory that includes said preselected memory cell as one of a plurality of memory cells integrated on a monolithic chip in a row and column matrix, each row being connected to an x decoder by an x line and each column being connected to a y decoder by a y line, the improvement comprising: a. means for simultaneously charging all x and y lines of said row and column matrix of memory cells; b. x coordinate and y coordinate decoding means for simultaneously discharging all of said charged x and y lines except those lines mutually connecting said preselected memory cell; and c. means for connecting said preselected cell to the computer input/output sense lines.
Claim 6
Dependent Claim
160 words
In a random access memory computer system wherein the central processing unit of the computer defines x and y coordinates of a preselected cross-coupled flip-flop memory cell to be operated on by the computer and translates these coordinates to an insulated gate field effect transistor memory that includes said preselected memory cell as one of a plurality of memory cells integrated on a monolithic chip in a row and column matrix, each row being connected to an x decoder by an x line and each column being connected to a y decoder by a y line, the improvement comprising: a. means for simultaneously charging all x and y lines of said row and column matrix of memory cells; b. x coordinate and y coordinate decoding means for simultaneously discharging all of said charged x and y lines except those lines mutually connecting said preselected memory cell; and c. means for connecting said preselected cell to the computer input/output sense lines.
Claim 7
Dependent Claim
79 words
The random access memory system as set forth in claim 4 wherein said means for simultaneously charging all x and y lines of said matrix comprises an insulated gate field effect transistor in series with each of said lines, said transistor being operative in response to a gate signal, to apply a high voltage to said line, whereby gate signals simultaneously applied to each of said transistors effects a simultaneous charging of all of said x and y lines.
Claim 8
Dependent Claim
96 words
The random access memory system as set forth in claim 4 wherein said x coordinate and y coordinate decoding means for discharging all but said preselected x and y lines comprises for each x and y line of the matrix a first insulated gate field effect transistor connecting the line to an OR circuit that includes a plurality of insulated gate field effect transistors, said OR circuit being operative when said first transistor is biased on, to discharge said lines to ground when at least one of said transistors of said OR circuit is biased on.
Claim 9
Dependent Claim
44 words
The memory sYstem as set forth in claim 4 wherein said means for connecting to the computer input/output sense lines comprises a pair of conductors connected to said chip, said pair of conductors being connected through gating means to each column of memory cells.
Claim 10
Dependent Claim
49 words
A memory system as set forth in claim 7 wherein said gating means comprises for each column of the memory matrix an insulated gate field effect transistor connected in series with each of said sense lines, said transistors having gate leads commonly connected to said y coordinate decoding means.
Claim 11
Dependent Claim
132 words
An insulated gate field effect high speed random access memory circuit integrated on a monolithic chip directly compatible with transistor-transistor-logic circuitry comprising in combination: a. a plurality of cross-coupled flip-flop memory cells arranged in a matrix, each cell of cross-coupled flip-flop, the matrix being defined by x and y coordinates, each of said cells having insulated gate field effect isolation means for isolating said cell from other cells of said matrix; b. x coordinate decoding means; c. y coordinate decoding means; d. means for simultaneously addressing all of said cells of said matrix thereby to recharge the capacitance of each cell; e. means for selecting a preselected cell to be operated on by the computer; and f. means for connecting said preselected cell to the computer sense lines to be operated on.
Claim 12
Dependent Claim
132 words
An insulated gate field effect high speed random access memory circuit integrated on a monolithic chip directly compatible with transistor-transistor-logic circuitry comprising in combination: a. a plurality of cross-coupled flip-flop memory cells arranged in a matrix, each cell of cross-coupled flip-flop, the matrix being defined by x and y coordinates, each of said cells having insulated gate field effect isolation means for isolating said cell from other cells of said matrix; b. x coordinate decoding means; c. y coordinate decoding means; d. means for simultaneously addressing all of said cells of said matrix thereby to recharge the capacitance of each cell; e. means for selecting a preselected cell to be operated on by the computer; and f. means for connecting said preselected cell to the computer sense lines to be operated on.
Claim 13
Dependent Claim
41 words
The memory circuit of claim 9 wherein said x decode means and y decode means are comprised of a plurality of insulated gate field effect transistors connected as an OR circuit, said transistors having gating levels directly compatible with transistor-transistor-logic outputs.
Claim 14
Dependent Claim
51 words
The memory circuit of claim 9 wherein said means for connecting selected cells to the computer comprises a pair of connectors making contact between said chip and circuitry external to said chip, said pair of connectors serving as computer input/output sense lines and a source of voltage for said memory cells.
Claim 15
Dependent Claim
36 words
The memory circuit of claim 9 wherein insulated gate field effect transistor switching means are formed on said chip for selecting whether read or write computer operations are to be performed on said selected memory cell.
Claim 16
Dependent Claim
93 words
In a random access memory matrix comprising x coordinate lines connecting rows of memory cells and y coordinate lines connecting columns of memory cells, a method for addressing a preselected cell of said matrix wherein the improvement comprises the steps of: a. simultaneously bringing high all of the x coordinate and y coordinate lines of the memory matrix thereby to recharge the capacitance of each memory cell of said matrix; and b. discharging all of said lines except the x coordinate line and the y coordinate line mutually connecting said preselected memory cell.
Claim 17
Dependent Claim
93 words
In a random access memory matrix comprising x coordinate lines connecting rows of memory cells and y coordinate lines connecting columns of memory cells, a method for addressing a preselected cell of said matrix wherein the improvement comprises the steps of: a. simultaneously bringing high all of the x coordinate and y coordinate lines of the memory matrix thereby to recharge the capacitance of each memory cell of said matrix; and b. discharging all of said lines except the x coordinate line and the y coordinate line mutually connecting said preselected memory cell.
Claim 18
Dependent Claim
23 words
The method as set forth in claim 13 wherein each of said memory cells is comprised of four insulated gate field effect transistors.
Claim 19
Dependent Claim
131 words
The method as set forth in claim 13 wherein the step of discharging all but certain preselected lines is further characterized by the steps of: a. biasing on respective first insulated gate field effect transistors connecting each x and y line to a respective OR circuit defined by a plurality of insulated gate field effect transistors having source terminals commonly connected to ground and having gate leads connected to transistor-transistor-logic outputs from an address register of a computer; and b. simultaneously applying coded signals from said address register to the gate terminals of the insulated gate field effect transistors making up said OR circuits whereby when at least one of said transistors of said OR circuit is biased on, the corresponding line connected to said OR circuit is discharged to ground.
References Cited (Backward Citations)
US3541530A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-12-19 | 1976-06-19 | 1976-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-12-19 | 1980-06-19 | 1980-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-12-19 | 1984-06-19 | 1984-12-19 | $7700.00 | Window Closed / Lapsed |