US3609712A
Expired / Lapsed
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Insulated gate field effect transistor memory array
Assignee: International Business Machines Corp
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Filing: 1969-01-15
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Granted: 1971-09-28
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Expires: 1989-01-15
Abstract
Abstract A bit oriented integrated circuit insulated gate field effect transistor memory array is disclosed which includes decoding on a semiconductor chip for both word and bit lines. Decoders which incorporate a combination of NOR logic elements and inverters provide for selection of a pair of bit lines and a single word line such that information can be written into a field effect transistor bistable circuit memory cell associated with these word and bit lines. Decoder controlled bit line switches in the form of field effect transistors are enabled to close the circuit between the bit driver and a column of memory cells. Also disclosed is a bit line biasing technique which eliminates the possibility of false writing into unselected memory cells. This is accomplished by applying a voltage via a resistance to the bit lines or by intermittently applying an appropriate voltage to the bit conductors associated with unselected memory cells.
Inventors
- 👤 Robert H Dennard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 19:24
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
29 words
A bit-oriented memory array according to claim 1 wherein said bit line biasing means includes a voltage source and switching means coupled between said source and said bit conductors.
Claim 2
Dependent Claim
33 words
A bit-oriented memory array according to claim 2 further including means coupled to said switching means for energizing said switching means to periodically apply a voltage from said source to said bit conductors.
Claim 3
Dependent Claim
15 words
A bit-oriented memory array according to claim 2 wherein said switching means is a transistor.
Claim 4
Dependent Claim
16 words
A bit-oriented memory array according to claim 4 wherein said transistor is a field effect transistor.
Claim 5
Dependent Claim
29 words
A bit-oriented memory according to claim 1 wherein said bit line biasing means includes a voltage source and high impedance means coupled between said source and said bit conductors.
Claim 6
Dependent Claim
17 words
A bit-oriented memory array according to claim 6 wherein said high impedance means is a resistive element.
Claim 7
Dependent Claim
32 words
A bit-oriented memory array according to claim 1 further including decoding means adapted to select one of said word conductors said word conductor being associated with a group of said memory cells.
Claim 8
Dependent Claim
26 words
A bit-oriented memory array according to claim 8 further including means connected to said word conductors for applying a potential to said group of memory cells.
Claim 9
Dependent Claim
24 words
A bit-oriented memory array according to claim 8 wherein said decoding means includes a switchable element serially disposed in each of said word conductors.
Claim 10
Dependent Claim
17 words
A bit-oriented memory array according to claim 10 wherein said switchable element is a field effect transistor.
Claim 11
Dependent Claim
90 words
A bit-oriented memory array according to claim 8 wherein said decoding means further includes a plurality of signal leads, a plurality of signal inverting means, one of said signal inverting means being connected to one of said signal leads, a plurality of logic circuits having as many inputs as there are signal leads, each of said inputs being connected to a combination of signal leads and signal inverting means such that one of said logic circuits provides an output when said signal leads are energized with a predetermined voltage pattern.
Claim 12
Dependent Claim
89 words
A bit-oriented memory array according to claim 12 wherein said signal inverting means is an inverter circuit comprising a pair of field effect transistors serially disposed between a source of potential and ground, one of said field effect transistors being biased in the ON condition to apply the voltage of said source at a node between said pair of transistors, the other of said transistors biased in the OFF condition being responsive to a signal on its gate to reduce the voltage at said node to substantially zero volts.
Claim 13
Dependent Claim
148 words
A bit-oriented memory array according to claim 12 wherein said logic circuits are NOR circuits and comprise: a source of voltage, a gated load field effect transistor disposed in series with said source, a group of gated field effect transistors, each of the group being disposed in parallel with the others and in series with said load field effect transistor, means coupled to said gated load field effect transistor for applying the voltage of said source at a node between said gated load field effect transistor and said group of gated field effect transistors at selected intervals, said inputs being connected to said group of gated field effect transistors, one input to one gate, respectively, the voltage at said node being maintained during said selected intervals when the inputs to the gates of said group of field effect transistors maintain each of said group in the OFF condition.
Claim 14
Dependent Claim
43 words
A bit-oriented memory array according to claim 14 wherein said means for applying the voltage of said source at a node at selected intervals includes a pulsed source connected to said load field effect transistor which turns said load field effect transistor ON.
Claim 15
Dependent Claim
35 words
A bit-oriented memory array according to claim 1 further including decoding means adapted to select a pair of said bit conductors, said pair of bit conductors being associated with a portion of said memory cells.
Claim 16
Dependent Claim
26 words
A bit-oriented memory array according to claim 1 further including means connected to said bit conductors for applying potentials to said portion of said memory cells.
Claim 17
Dependent Claim
24 words
A bit-oriented memory array according to claim 17 wherein said decoding means includes a switchable element serially disposed in each of said bit conductors.
Claim 18
Dependent Claim
17 words
A bit-oriented memory array according to claim 18 wherein said switchable element is a field effect transistor.
Claim 19
Dependent Claim
90 words
A bit-oriented memory array according to claim 16 wherein said decoding means includes a plurality of signal leads, a plurality of signal inverting means, one of said signal inverting means being connected to one of said sIgnal leads, a plurality of logic circuits having as many inputs as there are signal leads, each of said inputs being connected to a combination of signal leads and signal inverting means such that only one of said logic circuits provides an output when said signal leads are energized with a predetermined voltage pattern.
Claim 20
Dependent Claim
89 words
A bit-oriented memory array according to claim 20 wherein said signal inverting means is an inverter circuit comprising a pair of field effect transistors serially disposed between a source of potential and ground, one of said field effect transistors being biased in the ON condition to apply the voltage of said source at a node between said pair of transistors, the other of said transistors biased in the OFF condition being responsive to a signal on its gate to reduce the voltage at said node to substantially zero volts.
Claim 21
Dependent Claim
147 words
A bit-oriented memory array according to claim 20 wherein said logic circuits are NOR circuits and comprise: a source of voltage, a gated load field effect transistor disposed in series with said source, a group of gated field effect transistors each of the group being disposed in parallel with the others and in series with said load field effect transistor, means coupled to said gated load field effect transistor for applying the voltage of said source at a node between said gated load field effect transistor and said group of gated field effect transistor at selected intervals, inputs being connected to said group of gated field effect transistors, one input to one gate, respectively, the voltage at said node being maintained during said selected intervals when the inputs to the gates of said group of field effect transistors maintain each of said group in the OFF condition.
Claim 22
Dependent Claim
43 words
A bit-oriented memory array according to claim 22 wherein said means for applying the voltage of said source at a node at selected intervals includes a pulsed source connected to said load field effect transistor which turns said load field effect transistor ON.
Claim 23
Dependent Claim
64 words
A bit-oriented memory array which stores information in field effect transistor bistable circuits by charging the gate capacitance of one of the field effect transistors to the power supply voltage of said cell via word and bit conductors characterized by means for charging the bit conductor capacitance of said bit conductors to approximately said power-supply voltage during intervals when said bit conductors are unselected.
Claim 24
Dependent Claim
32 words
A bit-oriented memory according to claim 24 wherein said means for charging the bit conductor capacitance includes a source of voltage and means for electrically connecting said source to said bit conductors.
Claim 25
Dependent Claim
32 words
A bit-oriented memory according to claim 25 wherein said means for electrically connecting said source to said bit conductors includes a resistor disposed in series with said source and said bit conductors.
Claim 26
Dependent Claim
33 words
A bit-oriented memory according to claim 25 wherein said means for electrically connecting said source to said bit conductors includes a switchable transistor disposed in series with said source and said bit conductors.
Claim 27
Independent Claim
86 words
A method for eliminating false writing of unselected memory cells of a bit-oriented memory array each of which stores information in a field effect transistor bistable circuit by charging the gate capacitance of one of the field effect transistors of said bistable circuit to a given power supply voltage via word and bit conductor comprising the step of: applying a potential of approximately said given voltage to the bit conductors associated with unselected memory cells to charge up the bit conductor capacitance to said given voltage.
Claim 28
Dependent Claim
17 words
A method according to claim 28 wherein the step of applying a potential is carried out continuously.
Claim 29
Dependent Claim
17 words
A method according to claim 28 wherein the step of applying a potential is carried out intermittently.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-27 | 1975-03-29 | 1975-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-27 | 1979-03-29 | 1979-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-27 | 1983-03-29 | 1983-09-28 | $7700.00 | Window Closed / Lapsed |