US3795828A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Monolithic decoder circuit
Assignee: International Business Machines Corp
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Filing: 1973-03-08
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Granted: 1974-03-05
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Expires: 1993-03-08
Abstract
Abstract A monolithic decoder circuit provides a decode function with driving capabilities at opposite ports and requires only a single layer of metallization. The circuit comprises a plurality of gates each including a pair of transistors formed by emitter diffusions in a base area. Current switches are connected to the emitters of the transistors to provide inputs and emitter followers are connected to the bases of the transistors to provide outputs.
Inventors
- 👤 J Cavaliere
- 👤 D Mooney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 18:40
CPC Classifications
H; H03; H03M; H03M7/00; H10; H10B; H10B20/00; H10B20/10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/615
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
363 words
In a monolithic integrated decoder circuit in the form of an integral semiconductor chip including a plurality of first mutually-spaced semiconductor portions of a first conductivity type. a plurality of second semiconductor portions of a second conductivity type and each located within a respective one of said first portions, each of said second portions having therein a plurality of emitter regions of said first conductivity type, each of said first portions comprising a plurality of mutuallyspaced collector regions therein, each of said second portions comprising a plurality of mutuallyspaced base regions therein with each base region separated from a respective collector region by a first P-N junction and separated from a respective emitter region by a second P-N junction, whereby each first portion and the respective second portion therein and the respective emitter regions within said respective second portion constitute a row of transistors, the improvement comprising: a plurality of metal conductors each in ohmic contact with both a respective first portion and the respective second portion located within said respective first portion, and a plurality of subcollector regions of said first conductivity type and having an impurity concentration greater than that of said first portions and each located within a respective first portion and in conductive contact with the collector regions within said respective first portion, the collector regions of each row of transistors being connected to each other through relatively low resistance paths within the respective subcollector region, the collector region of at least one transistor of each row being connected to the respective metal conductor through a path within said first portion, the base regions of each row of transistors being connected to each other through paths within the respective second portion, the base region of at least one transistor of each row being connected to the respective metal conductor through a path within said respective second portion, whereby the collector regions of the transistors of each row are connected to the base regions of the transistors of said row through semiconductive paths and the respective metal conductor so as to prevent said transistors from saturating and thereby to prevent saturation effects from delaying the switching operation of said transistors.
Claim 2
Dependent Claim
363 words
In a monolithic integrated decoder circuit in the form of an integral semiconductor chip including a plurality of first mutually-spaced semiconductor portions of a first conductivity type. a plurality of second semiconductor portions of a second conductivity type and each located within a respective one of said first portions, each of said second portions having therein a plurality of emitter regions of said first conductivity type, each of said first portions comprising a plurality of mutuallyspaced collector regions therein, each of said second portions comprising a plurality of mutuallyspaced base regions therein with each base region separated from a respective collector region by a first P-N junction and separated from a respective emitter region by a second P-N junction, whereby each first portion and the respective second portion therein and the respective emitter regions within said respective second portion constitute a row of transistors, the improvement comprising: a plurality of metal conductors each in ohmic contact with both a respective first portion and the respective second portion located within said respective first portion, and a plurality of subcollector regions of said first conductivity type and having an impurity concentration greater than that of said first portions and each located within a respective first portion and in conductive contact with the collector regions within said respective first portion, the collector regions of each row of transistors being connected to each other through relatively low resistance paths within the respective subcollector region, the collector region of at least one transistor of each row being connected to the respective metal conductor through a path within said first portion, the base regions of each row of transistors being connected to each other through paths within the respective second portion, the base region of at least one transistor of each row being connected to the respective metal conductor through a path within said respective second portion, whereby the collector regions of the transistors of each row are connected to the base regions of the transistors of said row through semiconductive paths and the respective metal conductor so as to prevent said transistors from saturating and thereby to prevent saturation effects from delaying the switching operation of said transistors.
Claim 3
Dependent Claim
149 words
A monolithic integrated decoder circuit as set forth in claim 1 wherein each of said first portions and the respective second portion therein extend longitudinally, each metal conductor being in contact with one end of the respective first portion and with one end of the respective second portion, a second plurality of metal conductors each in ohmic contact with both the opposite end of a respective first portion and the opposite end of the respective second portion located within said respective first portion, a first plurality of output means each connected to a respective one of said first-recited metal conductors connected to said one ends of said first and second portions, and a second plurality of output means each connected to a respective one of said second plurality of metal conductors, whereby each row of transistors of said decoder circuit is provided with driving capabilities at opposite ends thereof.
Claim 4
Dependent Claim
78 words
A monolithic integrated decoder circuit as set forth in claim 2 and comprising a plurality of inputs for signals to be decoded, a plurality of current switches each including a pair of transistors each having a collector and having an emitter of one transistor of the pair coupled to the emitter of the other transistor of the pair, means connecting said inputs to said current switches, and means connecting said current switch transistor collectors to said emitter regions.
Claim 5
Dependent Claim
66 words
A monolithic integrated decoder circuit as set forth in claim 3 wherein said output means comprise a plurality of emitter-follower transistors each having a base and an emitter, means connecting each of said metal conductors to the base of a respective one of said emitter-follower transistors, a plurality of outputs, and means connecting each of said emitter-follower transistor emitters to a respective one of said outputs.
Claim 6
Dependent Claim
78 words
A monolithic integrated decoder circuit as set forth in claim 1 and comprising a plurality of inputs for signals to be decoded, a plurality of current switches each including a pair of transistors each having a collector and having an emitter of one transistor of the pair coupled to the emitter of the other transistor of the pair, means connecting said inputs to said current switches, and means connecting said current switch transistor collectors to said emitter regions.
Claim 7
Dependent Claim
66 words
A monolithic integrated decoder circuit as set forth in claim 1 wherein said output means comprise a plurality of emitter-follower transistors each having a base and an emitter, means connecting each of said metal conductors to the base of a respective one of said emitter-follower transistors, a plurality of outputs, and means connecting each of said emitter-follower transistor emitters to a respective one of said outputs.
Claim 8
Dependent Claim
320 words
In a monolithic integrated decoder circuit in the form of an integral semiconductor chip including a first semiconductor portion of a first conductivity type, a second semiconductor portion of a second conductivity type and located within said first portion, said second portion having therein a plurality of emitter regions of said first conductivity type, said first portion comprising a plurality of mutually-spaced collector regions therein, said second portion comprising a plurality of mutually-spaced base regions therein with each base region separated from a respective collector region by a first P-N junction and separated from a respective emitter region by a second P-N junction, whereby said first portion and the second portion therein and the emitter regions within said second portion constitute a row of transistors, the improvement comprising: a metal conductor in ohmic contact with both said first portion and said second portion, and a subcollector region of said first conductivity type and having an impurity concentration greater than that of said first portion and located within said first portion and in conductive contact with the collector regions within said first portion, the collector regions of said row of transistors being connected to each other through relatively low resistance paths within the subcollector region, the collector region of at least one transistor of the row being connected to the metal conductor through a path within said first portion, the base regions of the row of transistors being connected to each other through paths within the second portion, the base region of at least one transistor of each row being connected to the metal conductor through a path within said second portion, whereby the collector regions of the transistors of the row are connected to the base regions of said transistors through semiconductor paths and the respective metal conductor so as to prevent said transistors from saturating and thereby to prevent saturation effects from delaying the switching operation of said transistors.
Claim 9
Dependent Claim
320 words
In a monolithic integrated decoder circuit in the form of an integral semiconductor chip including a first semiconductor portion of a first conductivity type, a second semiconductor portion of a second conductivity type and located within said first portion, said second portion having therein a plurality of emitter regions of said first conductivity type, said first portion comprising a plurality of mutually-spaced collector regions therein, said second portion comprising a plurality of mutually-spaced base regions therein with each base region separated from a respective collector region by a first P-N junction and separated from a respective emitter region by a second P-N junction, whereby said first portion and the second portion therein and the emitter regions within said second portion constitute a row of transistors, the improvement comprising: a metal conductor in ohmic contact with both said first portion and said second portion, and a subcollector region of said first conductivity type and having an impurity concentration greater than that of said first portion and located within said first portion and in conductive contact with the collector regions within said first portion, the collector regions of said row of transistors being connected to each other through relatively low resistance paths within the subcollector region, the collector region of at least one transistor of the row being connected to the metal conductor through a path within said first portion, the base regions of the row of transistors being connected to each other through paths within the second portion, the base region of at least one transistor of each row being connected to the metal conductor through a path within said second portion, whereby the collector regions of the transistors of the row are connected to the base regions of said transistors through semiconductor paths and the respective metal conductor so as to prevent said transistors from saturating and thereby to prevent saturation effects from delaying the switching operation of said transistors.
Claim 10
Dependent Claim
117 words
A monolithic integrated decoder circuit as set forth in claim 7 wherein said first portion and the second portion therein extend longitudinally, said metal conductor being in contact with one end of the first portion and with one end of the second portion, a second metal conductor in ohmic contact with both the opposite end of the first portion and the opposite end of the second portion, a first output means connected to said first-recited metal conductor connected to said one ends of said first and second portions, and a second output means connected to said second metal conductor, whereby said row of transistors of said decoder circuit is provided with driving capabilities at opposite ends thereof.
Claim 11
Dependent Claim
78 words
A monolithic integrated decoder circuit as set forth in claim 8 and comprising a plurality of inputs for signals to be decoded, a plurality of current switches each including a pair of transistors each having a collector and having an emitter of one transistor of the pair coupled to the emitter of the other transistor of the pair, means connecting said inputs to said current switches, and means connecting said current switch transistor collectors to said emitter regions.
Claim 12
Dependent Claim
66 words
A monolithic integrated decoder circuit as set forth in claim 9 wherein said output means comprise a plurality of emitter-follower transistors each having a base and an emitter, means connecting each of said metal conductors to the base of a respective one of said emitter-follower transistors, a plurality of outputs, and means connecting each of said emitter-follower transistor emitters to a respective one of said outputs.
Claim 13
Dependent Claim
78 words
A monolithic integrated decoder circuit as set forth in claim 7 and comprising a plurality of inputs for signals to be decoded, a plurality of current switches each including a pair of transistors each having a collector and having an emitter of one transistor of the pair coupled to the emitter of the other transistor of the pair, means connecting said inputs to said current switches, and means connecting said current switch transistor collectors to said emitter regions.
Claim 14
Dependent Claim
66 words
A monolithic integrated decoder circuit as set forth in claim 7 wherein said output means comprise a plurality of emitter-follower transistors each having a base and an emitter, means connecting each of said metal conductors to the base of a respective one of said emitter-follower transistors, a plurality of outputs, and means connecting each of said emitter-follower transistor emitters to a respective one of said outputs.
Claim 15
Dependent Claim
359 words
In a monolithic integrated decoder circuit in the form of an integral semiconductor chip including a plurality of first mutually-spaced semiconductor portions of a first conductivity type, a plurality of second semiconductor portions of a second conductivity type and each located within a respective one of said first portions, each of said second portions having therein a plurality of emitter regions of said first conductivity type, each of said fIrst portions comprising a plurality of mutually-spaced collector regions therein, each of said second portions comprising a plurality of mutually-spaced base regions therein with each base region separated from a respective collector region by a first P-N junction and separated from a respective emitter region by a second P-N junction, whereby each first portion and the respective second portion therein and the respective emitter regions within said respective second portion constitute a row of transistors, the improvement comprising: a plurality of conductive means each connecting a respective first portion and the respective second portion located within said respective first portion, and a plurality of subcollector regions of said first conductivity type and having an impurity concentration greater than that of said first portions and each located within a respective first portion and in conductive contact with the collector regions within said respective first portion, the collector regions of each row of transistors being connected to each other through relatively low resistance paths within the respective subcollector region, the collector region of at least one transistor of each row being connected to the respective conductive means through a path within said first portion, the base regions of each row of transistors being connected to each other through paths within the respective second portion, the base region of at least one transistor of each row being connected to the respective conductive means through a path within said respective second portion, whereby the collector regions of the transistors of each row are connected to the base regions of the transistors of said row through semiconductive paths and the respective conductive means so as to prevent said transistors from saturating and thereby to prevent saturation effects from delaying the switching operation of said transistors.
Claim 16
Dependent Claim
359 words
In a monolithic integrated decoder circuit in the form of an integral semiconductor chip including a plurality of first mutually-spaced semiconductor portions of a first conductivity type, a plurality of second semiconductor portions of a second conductivity type and each located within a respective one of said first portions, each of said second portions having therein a plurality of emitter regions of said first conductivity type, each of said fIrst portions comprising a plurality of mutually-spaced collector regions therein, each of said second portions comprising a plurality of mutually-spaced base regions therein with each base region separated from a respective collector region by a first P-N junction and separated from a respective emitter region by a second P-N junction, whereby each first portion and the respective second portion therein and the respective emitter regions within said respective second portion constitute a row of transistors, the improvement comprising: a plurality of conductive means each connecting a respective first portion and the respective second portion located within said respective first portion, and a plurality of subcollector regions of said first conductivity type and having an impurity concentration greater than that of said first portions and each located within a respective first portion and in conductive contact with the collector regions within said respective first portion, the collector regions of each row of transistors being connected to each other through relatively low resistance paths within the respective subcollector region, the collector region of at least one transistor of each row being connected to the respective conductive means through a path within said first portion, the base regions of each row of transistors being connected to each other through paths within the respective second portion, the base region of at least one transistor of each row being connected to the respective conductive means through a path within said respective second portion, whereby the collector regions of the transistors of each row are connected to the base regions of the transistors of said row through semiconductive paths and the respective conductive means so as to prevent said transistors from saturating and thereby to prevent saturation effects from delaying the switching operation of said transistors.
Claim 17
Dependent Claim
145 words
A monolithic integrated decoder circuit as set forth in claim 13 wherein each of said first portions and the respective second portion therein extend longitudinally, each conductive means being in contact with one end of the respective first portion and with one end of the respective second portion, a second plurality of conductive means each connecting the opposite end of a respective first portion and the opposite end of the respective second portion located within said respective first portion, a first plurality of output means each connected to a respective one of said first-recited conductive means connected to said one ends of said first and second portions, and a second plurality of output means each connected to a respective one of said second plurality of conductive means, whereby each row of transistors of said decoder circuit is provided with driving capabilities at opposite ends thereof.
Claim 18
Dependent Claim
78 words
A monolithic integrated decoder circuit as set forth in claim 14 and comprising a plurality of inputs for signals to be decoded, a plurality of current switches each including a pair of transistors each having a collector and having an emitter of one transistor of the pair coupled to the emitter of the other transistor of the pair, means connecting said inputs to said current switches, and means connecting said current switch transistor collectors to said emitter regions.
Claim 19
Dependent Claim
66 words
A monolithic integrated decoder circuit as set forth in claim 15 wherein said output means comprise a plurality of emitter-follower transistors each having a base and an emitter, means connecting each of said conductive means to the base of a respective one of said emitter-follower transistors, a plurality of outputs, and means connecting each of said emitter-follower transistor emitters to a respective one of said outputs.
Claim 20
Dependent Claim
78 words
A monolithic integrated decoder circuit as set forth in claim 13 and comprising a plurality of inputs for signals to be decoded, a plurality of current switches each including a pair of transistors each having a collector and having an emitter of one transistor of the pair coupled to the emitter of the other transistor of the pair, means connecting said inputs to said current switches, and means connecting said current switch transistor collectors to said emitter regions.
Claim 21
Dependent Claim
66 words
A monolithic integrated decoder circuit as set forth in claim 13 wherein said output means comprise a plurality of emitter-follower transistors each having a base and an emitter, means connecting each of said conductive means to the base of a respective one of said emitter-follower transistors, a plurality of outputs, and means connecting each of said emitter-follower transistor emitters to a respective one of said outputs.
References Cited (Backward Citations)
US3753005A
Cited
US3587052A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-03-04 | 1977-09-03 | 1978-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-03-04 | 1981-09-03 | 1982-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-03-04 | 1985-09-03 | 1986-03-05 | $7700.00 | Window Closed / Lapsed |