US3753005A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit comprising strip-like conductors
Assignee: US Philips Corp
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Filing: 1971-06-03
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Granted: 1973-08-14
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Expires: 1991-06-03
Abstract
Abstract An integrated circuit using ETL gates especially useful for code conversion is described. All of the input transistors of the gate having interconnected emitters and interconnected collectors. The inputs are made to the base regions and are supplied by means of a series of parallel, strip-like conductors on top of the circuit and passing over the input transistors. At least some of the input transistors have elongated base regions which extend perpendicular to the direction of the strip conductors so as to locate the base contact for the base region directly underneath the conductor to which it is connected. Space is provided between the conductors for the emitter interconnections and for connection to a coupling resistor. The arrangement described avoids many of the crossovers of the input conductors required in the prior art arrangement.
Inventors
- 👤 U Bertram
- 👤 H Hoffman
- 👤 H Neuhaus
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:01
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
189 words
An integrated circuit comprising a semiconductor body containing at least one logic gate, said gate comprising plural input transistors each having emitter, base, and collector regions, means interconnecting the emitter regions of the plural input transistors, means interconnecting the collector regions of the plural input transistors, an insulating layer on the semiconductor body, input means connected to the base regions of the plural input transistors and comprising plural parallel spaced strip-like connection conductors on the insulating layer and extending over the plural input transistors, and means connecting each of the connection conductors through a hole in the insulating layer, to respective base regions of the underlying transistors, at least two of the input transistors having elongated base regions extending in a direction perpendicular to the strip-like connection conductors such that the respective portions of said elongated base regions lie directly below and are connected to respective associated ones of said overlying connection conductors, said respective portions being unaligned with each other and at least one of the connection conductors being connected to one of said elongated base regions and extending over the other of said two elongated base regions.
Claim 2
Dependent Claim
189 words
An integrated circuit comprising a semiconductor body containing at least one logic gate, said gate comprising plural input transistors each having emitter, base, and collector regions, means interconnecting the emitter regions of the plural input transistors, means interconnecting the collector regions of the plural input transistors, an insulating layer on the semiconductor body, input means connected to the base regions of the plural input transistors and comprising plural parallel spaced strip-like connection conductors on the insulating layer and extending over the plural input transistors, and means connecting each of the connection conductors through a hole in the insulating layer, to respective base regions of the underlying transistors, at least two of the input transistors having elongated base regions extending in a direction perpendicular to the strip-like connection conductors such that the respective portions of said elongated base regions lie directly below and are connected to respective associated ones of said overlying connection conductors, said respective portions being unaligned with each other and at least one of the connection conductors being connected to one of said elongated base regions and extending over the other of said two elongated base regions.
Claim 3
Dependent Claim
23 words
An integrated circuit as set forth in claim 1, wherein the elongated base regions of said two input transistors have different longitudinal dimensions.
Claim 4
Dependent Claim
43 words
An integrated circuit as set forth in claim 2, wherein the emitter region of one of said two transistors is also elongated in a direction parallel to the elongation direction of its base region and extends toward said portion of the base region.
Claim 5
Dependent Claim
33 words
An integrated circuit as set forth in claim 3, wherein a resistor is connected to the interconnected emitters of the plural input transistors, said resistor extending underneath the connection conductors substantially perpendicular thereto.
Claim 6
Dependent Claim
23 words
An integrated circuit as set forth in claim 4, wherein an inverter transistor is provided having a base region connected to said resistor.
Claim 7
Dependent Claim
79 words
An integrated circuit as set forth in claim 4, wherein the connection conductors comprise two spaced apart groups of conductors, each Of said groups extending over half of the input transistors, the emitter regions of the input transistors extending to a space between the conductor groups and interconnection to said emitter regions are located within said space, said resistor having a connection point located within said space and said resistor extending from there to below one of the conductors.
Claim 8
Dependent Claim
16 words
An integrated circuit as set forth in claim 6, wherein each conductOr group comprises four conductors.
Claim 9
Dependent Claim
75 words
An integrated circuit as set forth in claim 1, wherein plural logic gates are provided in said semiconductor body, said plural logic gates being arranged in columns and said connection conductors being disposed so as to pass over said plural input transistors of each of the plural logic gates, and all of the input transistors have respective elongated base and emitter contacts that are spaced apart in the longitudinal direction of the elongated base regions.
Claim 10
Dependent Claim
19 words
An integrated circuit comprising plural logic gates as set forth in claim 1 arranged to form a code-converting circuit.
References Cited (Backward Citations)
US3284677A
Cited
US3292012A
Cited
US3381270A
Cited
US3518449A
Cited
US3448344A
Cited
US3402330A
Cited
US3506815A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-13 | 1977-02-12 | 1977-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-13 | 1981-02-12 | 1981-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-13 | 1985-02-12 | 1985-08-14 | $7700.00 | Window Closed / Lapsed |