US3587052A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor matrix
Assignee: Tektronix Inc
•
Filing: 1968-10-28
•
Granted: 1971-06-22
•
Expires: 1988-10-28
Abstract
Abstract In a matrix of transistors, base and emitter elements are interconnected in first and second groups wherein each transistor is identified by a unique combination of input connections with respect to the first and second groups. Transistors, the combined input values of which add to the same sum, have common collector output means for providing an adding function. In an integrated circuit construction, the common collector output means comprise adjoining isolation regions, wherein several transistors may be disposed along each isolation region. Means interconnecting transistor emitters in first groups comprise conductors connecting the emitters of no more than one transistor in each isolation region. Dual base terminals permit conductors, which comprise the means to interconnect the transistor base terminals in second groups, to extend in between first group conductors, and from a transistor in one isolation region to a transistor in another isolation region, avoiding crossunders and the like.
Inventors
- 👤 Michael H Metcalf
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 20:14
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/491; G06F7/4912; G01; G01B; G01B11/00; G01B11/02; G01B11/06; G01B11/0616; G01B11/0625; H; H10; H10B; H10B20/00; H10B20/10; H10D; H10D99/00; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30; G06F2207/00; G06F2207/491; G06F2207/49195
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
145 words
An adding matrix comprising: a plurality of transistors each having a collector portion, a base portion, and an emitter portion, and input terminals separately connected to said emitter portions and base portions respectively, each transistor providing a collector output when both input terminals thereof receive a predetermined input, means interconnecting the emitter input terminals of said transistors in first groups corresponding respectively to first input values, means interconnecting the base input terminals of said transistors in second groups corresponding respectively to second input values, wherein each transistor is identified by a unique combination of input connections with respect to said first and second groups, ones of said transistors having common collector output means as the combined input values thereof add to the same sum, and means for providing an input to only a selected first group interconnecting means and a selected second group interconnecting means.
Claim 2
Dependent Claim
145 words
An adding matrix comprising: a plurality of transistors each having a collector portion, a base portion, and an emitter portion, and input terminals separately connected to said emitter portions and base portions respectively, each transistor providing a collector output when both input terminals thereof receive a predetermined input, means interconnecting the emitter input terminals of said transistors in first groups corresponding respectively to first input values, means interconnecting the base input terminals of said transistors in second groups corresponding respectively to second input values, wherein each transistor is identified by a unique combination of input connections with respect to said first and second groups, ones of said transistors having common collector output means as the combined input values thereof add to the same sum, and means for providing an input to only a selected first group interconnecting means and a selected second group interconnecting means.
Claim 3
Dependent Claim
21 words
The matrix according to claim 1 wherein said common collector output means comprise common collector output connections joining selected collector portions.
Claim 4
Dependent Claim
87 words
The matrix according to claim 1 wherein said common collector output means comprise adjacent collector regions in a semiconductor layer of a monolithic integrated circuit structure, said collector regions being provided by adjacent isolation regions in said semiconductor layer, ones of said base portions being disposed along said isolation regions to provide one or more transistors along each such isolation region according to the number of input combinations which result in the same sum, with each base portion separating an emitter portion from the corresponding collector region.
Claim 5
Dependent Claim
55 words
The matrix according to claim 3 wherein said means interconnecting the input terminals in first groups comprises first conductors insulatably crossing said isolation regions and making connection only with emitter input terminals of transistors in the corresponding groups, wherein such first conductor connects emitter input terminals of not more than one transistor per isolation region.
Claim 6
Dependent Claim
120 words
The matrix according to claim 4 wherein said means for interconnecting base terminals of said transistors in second groups comprise second conductors disposed in between said first conductors, in substantially the same plane therewith, connecting a base input terminal disposed in one isolation region with a base terminal in the next adjacent isolation region of a transistor the base of which is interconnected in a different first group by a different first conductor, at least ones of said base portions being provided with a pair of base terminals on each side of an emitter portion and to which said second conductors are connected in order that said second conductors may be located in between first conductors without crossing first conductors.
Claim 7
Dependent Claim
45 words
The matrix according to claim 5 wherein said first and second conductors are separated from said semiconductor layer by a layer of oxide insulation having apertures through which said conductors make connection with said emitter portions and said base portions, to form input terminals therefor.
Claim 8
Dependent Claim
76 words
The matrix according to claim 1 further including a second and substantially similar matrix also having means interconnecting the emitter input terminals thereof in first groups as well as means interconnecting the base input terminals thereof in second groups to provide another column of addition, ones of said groups of the second matrix receiving the outputs of said common collector output means of the first matrix for indicating a carry digit input to said second matrix.
Claim 9
Dependent Claim
26 words
The apparatus according to claim 7 including means for receiving indication of the carry digit to shift inputs to the second matrix by one digit position.
Claim 10
Dependent Claim
139 words
A transistor matrix comprising: a plurality of transistors each having a collector portion, a base portion, and an emitter portion, and input terminals separately connected to said emitter portions and base portions respectively, each transistor providing a collector output when both input terminals thereof receive a predetermined input, means interconnecting the emitter input terminals of said transistors in first groups corresponding respectively to first input values, means interconnecting the base input terminals of said transistors in second groups corresponding respectively to second input values, wherein each transistor is identified by a unique combination of input connections with respect to said first and second groups, ones of said transistors having common collector output means to provide related coding information, and means for providing an input to only a selEcted first group interconnecting means and a selected second group interconnecting means.
Claim 11
Dependent Claim
139 words
A transistor matrix comprising: a plurality of transistors each having a collector portion, a base portion, and an emitter portion, and input terminals separately connected to said emitter portions and base portions respectively, each transistor providing a collector output when both input terminals thereof receive a predetermined input, means interconnecting the emitter input terminals of said transistors in first groups corresponding respectively to first input values, means interconnecting the base input terminals of said transistors in second groups corresponding respectively to second input values, wherein each transistor is identified by a unique combination of input connections with respect to said first and second groups, ones of said transistors having common collector output means to provide related coding information, and means for providing an input to only a selEcted first group interconnecting means and a selected second group interconnecting means.
Claim 12
Dependent Claim
74 words
The matrix according to claim 9 wherein said common collector output means comprise adjacent collector regions in a semiconductor layer of a monolithic integrated circuit structure, said collector regions being provided by adjacent isolation regions in said semiconductor layer, ones of said base portions being disposed along said isolation regions to provide one or more transistors along each such isolation region, with each base portion separating an emitter portion from the corresponding collector region.
Claim 13
Dependent Claim
55 words
The matrix according to claim 10 wherein said means interconnecting the input terminals in first groups comprises first conductors insulatably crossing said isolation regions and making connection only with emitter input terminals of transistors in the corresponding groups, wherein each first conductor connects emitter input terminals of not more than one transistor per isolation region.
Claim 14
Dependent Claim
120 words
The matrix according to claim 11 wherein said means for interconnecting base terminals of said transistors in second groups comprise second conductors disposed in between said first conductors in substantially the same plane therewith, connecting a base input terminal disposed in one isolation region with a base terminal in the next adjacent isolation region of a transistor the base of which is interconnected in a different first group by a different first conductor, at least ones of said base portions being provided with a pair of base terminals on each side of an emitter portion and to which said second conductors are connected in order that said second conductors may be located in between first conductors without crossing first conductors.
Claim 15
Dependent Claim
45 words
The matrix according to claim 12 wherein said first and second conductors are separated from said semiconductor layer by a layer of oxide insulation having apertures through which said conductors make connection with said emitter portions and said base portions to form input terminals therefor.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-21 | 1974-12-21 | 1975-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-21 | 1978-12-21 | 1979-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-21 | 1982-12-21 | 1983-06-22 | $7700.00 | Window Closed / Lapsed |