Patent US3781796A successfully refreshed from Google Patents.
US3781796A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Error detecting translator
Assignee: AT&T Inc
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Filing: 1972-10-16
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Granted: 1973-12-25
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Expires: 1992-10-16
Abstract
Abstract A signal translation circuit arrangement comprises two translators that operate according to different rules of action. The translators respond to each valid input signal representation by forming identical corresponding output signal representations and the translators respond to each invalid input signal representation by forming nonidentical output signal representations. Invalid input signal representations and circuit malfunctions are detected by comparing the output signals generated by the translators.
Inventors
- 👤 Smith N Kimbrough
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 10:24
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/085
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
231 words
A translating circuit arrangement comprising: a plurality of input terminals; a plurality of output terminals; first and second translators each comprising: a set oF input terminals, a set of output terminals, and circuitry for selectively energizing the said plurality of output terminals responsive to signals applied to the said set of input terminals; said plurality of input terminals of said arrangement connected to said sets of input terminals of said first and said second translators; said plurality of output terminals of said arrangement connected to said set of output terminals of said first translator; comparing means comprising: an error terminal, input terminals connected to said sets of output terminals of said first and of said second translators, and means for comparing output signals at the said sets of output terminals of said first and of said second translators and for generating an error signal when the said output signals are not identical; characterized in that, signals applied to said plurality of input terminals of said arrangement have a certain characteristic when valid; and said circuitry of said first translator and said circuitry of said second translator comprise: means for generating identical output signals at their respective set of output terminals in response to signals having said certain characteristic, and means for generating nonidentical output signals at their respective set of output terminals in response to signals not exhibiting said certain characteristic.
Claim 2
Dependent Claim
231 words
A translating circuit arrangement comprising: a plurality of input terminals; a plurality of output terminals; first and second translators each comprising: a set oF input terminals, a set of output terminals, and circuitry for selectively energizing the said plurality of output terminals responsive to signals applied to the said set of input terminals; said plurality of input terminals of said arrangement connected to said sets of input terminals of said first and said second translators; said plurality of output terminals of said arrangement connected to said set of output terminals of said first translator; comparing means comprising: an error terminal, input terminals connected to said sets of output terminals of said first and of said second translators, and means for comparing output signals at the said sets of output terminals of said first and of said second translators and for generating an error signal when the said output signals are not identical; characterized in that, signals applied to said plurality of input terminals of said arrangement have a certain characteristic when valid; and said circuitry of said first translator and said circuitry of said second translator comprise: means for generating identical output signals at their respective set of output terminals in response to signals having said certain characteristic, and means for generating nonidentical output signals at their respective set of output terminals in response to signals not exhibiting said certain characteristic.
Claim 3
Dependent Claim
130 words
A translating circuit arrangement in accordance with claim 1 characterized in that, said circuitry of said first translator comprises: a plurality of independent logic circuits individually connected to corresponding ones of said set of output terminals of said first translator and connected to those of said set of input terminals of said first translator that are defined as being active to generate an active signal on a connected output terminal; and said circuitry of said second translator comprises: a plurality of independent logic circuits individually connected to corresponding ones of said set of output terminals of said second translator and connected to those of said second set of input terminals of said second translator that are defined as being active to generate an inactive signal on a connected output terminal.
Claim 4
Dependent Claim
227 words
A translating circuit arrangement for use with one-out-of-n coded data, comprising: a plurality of input terminals; a plurality of output terminals; a first translator, comprising: a set of input terminals connected to said plurality of input terminals, and a set of output terminals connected to said plurality of output terminals; a second translator, comprising: a set of input terminals connected to said plurality of input terminals, and a set of output terminals; comparing means having an error terminal and connected to said sets of output terminals of said first and of said second translators comprising: means for comparing output signals at the said sets of output terminals and for generating an error signal when the said output signals are not identical; characterized in that, said first translator further comprises: a plurality of OR circuits individually connected to corresponding ones of said set of output terminals and connected to those of said set of input terminals that are defined as being active to generate an active signal on a connected output terminal; and said second translator further comprises: a plurality of NOR circuits individually connected to corresponding ones of said set of output terminals of said second translator and connected to those of said set of input terminals of said second translator that are defined as being active to generate an inactive signal on a connected output terminal.
Claim 5
Dependent Claim
227 words
A translating circuit arrangement for use with one-out-of-n coded data, comprising: a plurality of input terminals; a plurality of output terminals; a first translator, comprising: a set of input terminals connected to said plurality of input terminals, and a set of output terminals connected to said plurality of output terminals; a second translator, comprising: a set of input terminals connected to said plurality of input terminals, and a set of output terminals; comparing means having an error terminal and connected to said sets of output terminals of said first and of said second translators comprising: means for comparing output signals at the said sets of output terminals and for generating an error signal when the said output signals are not identical; characterized in that, said first translator further comprises: a plurality of OR circuits individually connected to corresponding ones of said set of output terminals and connected to those of said set of input terminals that are defined as being active to generate an active signal on a connected output terminal; and said second translator further comprises: a plurality of NOR circuits individually connected to corresponding ones of said set of output terminals of said second translator and connected to those of said set of input terminals of said second translator that are defined as being active to generate an inactive signal on a connected output terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-24 | 1977-06-25 | 1977-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-24 | 1981-06-25 | 1981-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-24 | 1985-06-25 | 1985-12-25 | $7700.00 | Window Closed / Lapsed |