US3710318A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Error detection circuit
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1971-11-22
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Granted: 1973-01-09
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Expires: 1991-11-22
Abstract
Abstract A logic circuit having nine input terminals uses four full adders and a NAND-gate to provide an output signal when signals are applied to any two or more of the input terminals.
Inventors
- 👤 W Powell
- 👤 J Powell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:01
CPC Classifications
H; H03; H03K; H03K19/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
152 words
A logic circuit which provides an output signal when more than one input signal is applied, but provides no output signal when less than two signals are applied, said circuit comprising: first, second, third and fourth binary full adders each having first, second and third input leads, a sum output lead and a carry-not output lead; a plurality of input terminals, each of said input terminals being connected to a corresponding one of said input leads of said first, said second and said third adders; and a NAND-gate having first, second, third and fourth input leads and an output lead, said carry-not output leads of said first, second, third and fourth adders each being connected to a corresponding one of said input leads of said gate, said sum output leads of said first, second and third adders each being connected to a corresponding one of said input leads of said fourth adder.
Claim 2
Dependent Claim
152 words
A logic circuit which provides an output signal when more than one input signal is applied, but provides no output signal when less than two signals are applied, said circuit comprising: first, second, third and fourth binary full adders each having first, second and third input leads, a sum output lead and a carry-not output lead; a plurality of input terminals, each of said input terminals being connected to a corresponding one of said input leads of said first, said second and said third adders; and a NAND-gate having first, second, third and fourth input leads and an output lead, said carry-not output leads of said first, second, third and fourth adders each being connected to a corresponding one of said input leads of said gate, said sum output leads of said first, second and third adders each being connected to a corresponding one of said input leads of said fourth adder.
Claim 3
Dependent Claim
238 words
A logic circuit which provides an output signal when more than one input signal is applied, but provides no output signal when less than two input signals are applied, said circuit comprising: first, second, third and fourth binary full adders each having first, second and third input leads and a sum, a sum-not, a carry and a carry-not output leads; a plurality of input terminals, each of said input terminals being coupled to a corresponding one of said input leads of said first, said second and said third adders; first, second, third, fourth, fifth and sixth inverters, said first, said second and said third inverters each being connected between said second adder and a corresponding one of said input leads of said second adder, said fourth, said fifth and said sixth inverters each being connected between said fourth adder and a corresponding one of said input leads of said fourth adder; and a NAND-gate having first, second, third and fourth input leads and an output lead, said carry-not output leads of said first and said third Adders and said carry output leads of said second and said fourth adders each being connected to a corresponding one of said input leads of said gate, said sum output leads of said first and said third adders and said sum-not output lead of said second adder each being connected to a corresponding one of said input leads of said fourth adder.
Claim 4
Dependent Claim
238 words
A logic circuit which provides an output signal when more than one input signal is applied, but provides no output signal when less than two input signals are applied, said circuit comprising: first, second, third and fourth binary full adders each having first, second and third input leads and a sum, a sum-not, a carry and a carry-not output leads; a plurality of input terminals, each of said input terminals being coupled to a corresponding one of said input leads of said first, said second and said third adders; first, second, third, fourth, fifth and sixth inverters, said first, said second and said third inverters each being connected between said second adder and a corresponding one of said input leads of said second adder, said fourth, said fifth and said sixth inverters each being connected between said fourth adder and a corresponding one of said input leads of said fourth adder; and a NAND-gate having first, second, third and fourth input leads and an output lead, said carry-not output leads of said first and said third Adders and said carry output leads of said second and said fourth adders each being connected to a corresponding one of said input leads of said gate, said sum output leads of said first and said third adders and said sum-not output lead of said second adder each being connected to a corresponding one of said input leads of said fourth adder.
References Cited (Backward Citations)
US3317753A
Cited
US3541348A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-09 | 1976-07-10 | 1977-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-09 | 1980-07-10 | 1981-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-09 | 1984-07-10 | 1985-01-09 | $7700.00 | Window Closed / Lapsed |