US3775191A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Modification of channel regions in insulated gate field effect transistors
Assignee: Nortel Networks Technology Corp
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Filing: 1971-06-28
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Granted: 1973-11-27
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Expires: 1991-06-28
Abstract
Abstract Method of producing channel regions in IGFET''s by implanting ions in the gate region through the gate, the gate of polycrystalline silicon material. The method both produces conducting channel regions and removes conducting channel regions. Enhancement mode and depletion mode transistors can be made. Other devices, such as resistors, can be formed simultaneously or sequentially by the implantation step.
Inventors
- 👤 K Mcquhae
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 21:00
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0163; H10D84/02; H10D84/03; H10D84/038; H10D99/00; Y; Y10; Y10S; Y10S148/00; Y10S148/053; Y10S148/122
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
39 words
A method as claimed in claim 1, for forming a depletion mode transistor, said substrate a p-type substrate, wherein the device is exposed to a beam of ions to form an n-channel beneath the gate in the unmaSked window.
Claim 2
Dependent Claim
40 words
A method as claimed in claim 1, for forming a depletion mode transistor, said silicon substrate an n-type substrate, wherein the device is exposed to a beam of ions to form a p-channel beneath the gate in the unmasked window.
Claim 3
Dependent Claim
46 words
A method as claimed in claim 1 for forming an enhancement mode transistor, said silicon substrate a p-type substrate of high resistivity, wherein the device is exposed to a beam of ions to implant ions beneath the gate to form a lower resistivity p-type channel region.
Claim 4
Independent Claim
303 words
A method of forming a transistor device comprising at least two insulated gate field effect transistors, each transistor having a gate, a source and a drain aligned with said gate, and having a conducting channel beneath the gate of one transistor, comprising the sequential steps of: growing a field oxide on a silicon substrate; removing the field oxide to form windows through to the substrate at the desired positions of the transistors; growing a layer of oxide on said substrate in said windows; depositing a layer of polycrystalline silicon material on said oxide to form a gate in each of said windows, the polycrystalline silicon in one window of a thickness to permit ion implantation beneath by a beam of ions, the thickness of the polycrystalline silicon in the other window sufficient to prevent ion implantation beneath by said beam; removing the polycrystalline silicon from all areas except where a gate is required; opening windows through each oxide at positions to define a periphery of each gate and to define positions for forming a source and a drain for each transistor, each window having an inner periphery coincident with the periphery of its associated gate; diffusing a dopant through said windows in the oxide to form said sources and drains and simultaneously doping said gates; applying a layer of field oxide over the layer of polycrystalline silicon; exposing the device to a beam of ions to implant ions beneath the gate in the window having the thinner layer of polycrystalline silicon to form a conducting channel beneath the gate and connecting the source and the drain; opening windows in the field oxide layer to provide access to each source, each drain and each gate layer of polycrystalline silicon; applying a metal to the device to form connections to said sources, drains and gates.
Claim 5
Dependent Claim
46 words
A method as claimed in claim 5, for forming a depletion mode transistor, said silicon substrate a p-type substrate, wherein the device is exposed to a beam of ions to form an n-channel beneath the gate in the window having the thinner layer of polycrystalline silicon.
Claim 6
Dependent Claim
46 words
A method as claimed in claim 5, for forming a depletion mode transistor, said silicon substrate an n-type substrate, wherein the device is exposed to a beam of ions to form a p-channel beneath the gate in the window having the thinner layer of polycrystalline silicon.
Claim 7
Dependent Claim
84 words
A method of forming a transistor device as claimed in claim 5, wherein following the step of diffusing the dopant through the windows in the gate oxide to form sources and drains, the layer of polycrystalline silicon in each window in the field oxide are reduced in width, whereby an exposure to the beam of ions implantation also occurs in said substrate to form extensions to said sources and drains, at the ends of the channels, to form perfectly self-aligned gates in the transistors.
Claim 8
Dependent Claim
43 words
A method as claimed in claim 8, for forming a depletion mode transistor, said silicon substrate a p-type substrate, wherein the device is exposed to a beam of ions to form an n-channel beneath the gate having the thinner layer of polycrystalline silicon.
Claim 9
Dependent Claim
46 words
A method as claimed in claim 8, for forming a depletion mode transistor, said silicon substrate an n-type substrate, wherein the device is exposed to a beam of ions to form a p-channel beneath the gate in the window having the thinner layer of polycrystalline silicon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-11-26 | 1977-05-28 | 1977-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-11-26 | 1981-05-28 | 1981-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-11-26 | 1985-05-28 | 1985-11-27 | $7700.00 | Window Closed / Lapsed |