Patent US1183486A successfully refreshed from Google Patents.
US3753236A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprogrammable peripheral controller
Assignee: Bull HN Information Systems Italia SpA
•
Filing: 1972-03-31
•
Granted: 1973-08-14
•
Expires: 1992-03-31
Abstract
Abstract A microprogrammable peripheral controller is provided in which the control store microinstruction format is compatible with the read/write memory data word format and the architecture is compatible with character oriented peripheral data formats. The controller is provided with a processor which enables word transfers in a single operation. The processor also has the capability of performing a large repertory of arithmetic and logic microinstructions, but this is made economical by limiting such operations, in general, to byte length operands. With this processing capability, the primary controller control functions can be performed economically for a wide range of perioherals. A common interface is provided for data and control information transfers between the controller and both peripheral devices and central processor ports. In general, adaptor units are required to provide compatibility between the controller and the CPU ports and peripheral interfaces, to provide data buffering, to support multiplexing and for any other special functions. The primary feature to which this disclosure is directed is processor architecutral features which effectively eliminate processor execution time for performing branching operations whereby processing speed is effectively increased by a factor of more than one third for many if not all control store programs. Controller economy and reliability is further advanced by the use of dual arithmetic/logic modules which serve as redundant elements for byte operations and word transfer elements for word transfer operations.
Inventors
- 👤 R Flynn
- 👤 M Porter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 20:59
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/226; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F9/26; G06F9/262; G06F9/264; G06F9/265
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
130 words
A microprogrammable processor comprising: A. processor means, including register means, for performing a repertory of arithmetic and logic operations; B. a microinstruction register, capable of holding a pair of microinstruction words in even and odd portions of said microinstruction register; C. a control store, connected to said microinstruction register, for providing even/odd pairs of microinstructions in parallel to said even and odd portions; D. a general purpose microinstruction decoder, responsive to the first word in said microinstruction register, for controlling said processor means; E. a branch microinstruction decoder, responsive to the second word in said microinstruction register, for enabling braching simultaneously with execution of the first microinstruction word in said microinstruction register; F. transfer means for selectively transferring said second word to the first word position of said microinstruction register.
Claim 2
Dependent Claim
130 words
A microprogrammable processor comprising: A. processor means, including register means, for performing a repertory of arithmetic and logic operations; B. a microinstruction register, capable of holding a pair of microinstruction words in even and odd portions of said microinstruction register; C. a control store, connected to said microinstruction register, for providing even/odd pairs of microinstructions in parallel to said even and odd portions; D. a general purpose microinstruction decoder, responsive to the first word in said microinstruction register, for controlling said processor means; E. a branch microinstruction decoder, responsive to the second word in said microinstruction register, for enabling braching simultaneously with execution of the first microinstruction word in said microinstruction register; F. transfer means for selectively transferring said second word to the first word position of said microinstruction register.
Claim 3
Dependent Claim
25 words
The microprogrammable processor of claim 1, wherein: F. said general purpose microinstruction decoder including means to respond to all branch type microinstructions as NOP microinstructions.
Claim 4
Dependent Claim
297 words
A microprogrammable processor comprising: A. a microinstruction register, having a first even portion for storing microinstructions from even locations in a control store, and a second, odd portion for storing microinstructions from odd numbered locations; B. a control store, connected to said microinstruction register, for providing even/odd pairs of microinstructions in parallel to said even and odd portions; C. a general purpose microinstruction decoder, connected to said microinstruction register even portion, for determining the operation specified by the microinstruction; D. a branch microinstruction decoder, connected to said microinstruction odd portion, for detecting a branch operation specified by the odd microinstruction; E. a control store address register connected to said control store for selecting pairs of microinstructions; F. address modification means connected to said control store address register and said microinstruction register for modifying the contents of said control store address register in accordance with codinG in said microinstruction register odd portion; G. branch control means, connected to said control store address register, for selectively modifying the contents thereof and gating the addressed microinstruction pair from said control store to said microinstruction register during execution of an even microinstruction following loading of a microinstruction pair into said microinstruction registers, in response to said branch decoder detecting a branch condition in the coding of an odd instruction; H. processor means, connected to said general microinstruction decoder, and including an accumulator register for performing a repertory of data processing functions in accordance with the contents of said microinstruction even portion; I. transfer means, interconnecting said even and odd microinstruction register portions and responsive to said branch microinstruction decoder, for selectively transferring the contents of the odd portion to the even portion of said microinstruction register during execution of an even microinstruction when said decoder does not select a branch operation.
Claim 5
Dependent Claim
297 words
A microprogrammable processor comprising: A. a microinstruction register, having a first even portion for storing microinstructions from even locations in a control store, and a second, odd portion for storing microinstructions from odd numbered locations; B. a control store, connected to said microinstruction register, for providing even/odd pairs of microinstructions in parallel to said even and odd portions; C. a general purpose microinstruction decoder, connected to said microinstruction register even portion, for determining the operation specified by the microinstruction; D. a branch microinstruction decoder, connected to said microinstruction odd portion, for detecting a branch operation specified by the odd microinstruction; E. a control store address register connected to said control store for selecting pairs of microinstructions; F. address modification means connected to said control store address register and said microinstruction register for modifying the contents of said control store address register in accordance with codinG in said microinstruction register odd portion; G. branch control means, connected to said control store address register, for selectively modifying the contents thereof and gating the addressed microinstruction pair from said control store to said microinstruction register during execution of an even microinstruction following loading of a microinstruction pair into said microinstruction registers, in response to said branch decoder detecting a branch condition in the coding of an odd instruction; H. processor means, connected to said general microinstruction decoder, and including an accumulator register for performing a repertory of data processing functions in accordance with the contents of said microinstruction even portion; I. transfer means, interconnecting said even and odd microinstruction register portions and responsive to said branch microinstruction decoder, for selectively transferring the contents of the odd portion to the even portion of said microinstruction register during execution of an even microinstruction when said decoder does not select a branch operation.
Claim 6
Dependent Claim
73 words
The microprogrammable processor of claim 6, further comprising: J. an indicator register, responsive to said processor means, in such a manner that the contents of the indicator register store information representing conditions produced in performing a data processing function, including a zero result indicator; K. conditional branch control means, connected to said indicator register and said branch control means, for selectively inhibiting the gating of the addressed microinstruction pair to said microinstruction register.
Claim 7
Dependent Claim
25 words
The microproagrammable processor of claim 6 wherein: J. said general purpose microinstruction decoder including means to respond to all branch type microinstructions as NOP microinstructions.
References Cited (Backward Citations)
US3629853A
Cited
US3474412A
Cited
US3387278A
Cited
US3430197A
Cited
US3562713A
Cited
US3570006A
Cited
US3551895A
Cited
US3559183A
Cited
US3538498A
Cited
US3614747A
Cited
US3577189A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-13 | 1977-02-12 | 1977-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-13 | 1981-02-12 | 1981-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-13 | 1985-02-12 | 1985-08-14 | $7700.00 | Window Closed / Lapsed |