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US3430197A Expired / Lapsed US ⏱️ 0.0 years remaining

Error correction circuit for digital recording systems

Assignee: TDK Micronas GmbH
•
Filing: 1965-10-21
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Granted: 1969-02-25
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Expires: 1985-10-21
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Abstract

No abstract record available.

Inventors

  • 👤 Thomas G Brown

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-22 22:00
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1032; G11C; G11C29/00; G11C29/70; G11C29/88

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 259 words
AN ERROR CORRECTION CIRCUIT FOR DIGITAL RECORDING SYSTEM COMPRISING: (A) A PLURALITY OF INDEPENDENT RECEIVING MEANS, ONE FOR EACH BIT OF A MULTIBIT CODE SIGNAL TO BE RECEIVED; (B) A PLURALITY OF VOLTAGE STORING MEANS CONNECTED RESPECTIVELY TO SAID RECEIVING MEANS AND EACH ADAPTED TO MAINTAIN THE PEAK VOLTAGE OF ITS RECEIVED SIGNAL FOR A PERIOD OF TIME; (C) A PLURALITY OF VOLTAGE CCMPARATORS, ONE FOR EACH STORING MEANS AND CONNECTED RESPECTIVELY THERETO AND ARRANGED TO RESPOND WHEN THE VOLTAGE OF THE SIGNAL STORED IN THE ASSOCIATED STORING MEANS EXCEEDS A PREDETERMINED THRESHOLD VALVE; (D) PARITY CHECKING MEANS CONNECTED TO SAID VOLTAGE COMPARATORS AND ADAPTED TO PRODUCE A "PARITY GOOD" SIGNAL WHEN THERE IS A CORRECT NUMBER OF CODE BITS IN THE OUTPUTS OF SAID VOLTAGE COMPARATORS AND TO PRODUCE A "PARITY BAD" SIGNAL WHEN THERE IS AN INCORRECT NUMBER OF CODE BITS IN THE OUTPUTS OF SAID VOLTAGE COMPARATORS; (E) INDIVIDUAL OUTPUT MEANS, ONE FOR EACH OF SAID VOLTAGE COMPARATORS; (F) GATING MEANS BETWEEN SAID VOLTAGE COMPARATORS AND SAID OUTPUT MEANS AND CONNECTED TO SAID PARITY CHECKING MEANS FOR DELIVERING THE SIGNALS ON THE OUTPUTS OF SAID VOLTAGE COMPARATORS TO SAID OUTPUT MEANS IN RESPONSE TO A "PARITY GOOD" SIGNAL FROM SAID PARITY CHECKING MEANS; (G) MEANS CONNECTED TO SAID PARITY CHECKING MEANS AND RESPONSIVE TO A "PARITY BAD" SIGNAL THEREFROM FOR GRADUALLY REDUCING THE EFFECTIVE THRESHOLD VALUE OF SAID VOLTAGE COMPARATORS, AND (H) MEANS THEREAFTER RESPONSIVE TO A "PARITY GOOD" SIGNAL FROM SAID PARITY CHECKING MEANS FOR DISABLING SAID THRESHOLD-VALUE-REDUCING MEANS AND FOR ENABLING SAID GATING MEANS.
Claim 2
Dependent Claim 259 words
AN ERROR CORRECTION CIRCUIT FOR DIGITAL RECORDING SYSTEM COMPRISING: (A) A PLURALITY OF INDEPENDENT RECEIVING MEANS, ONE FOR EACH BIT OF A MULTIBIT CODE SIGNAL TO BE RECEIVED; (B) A PLURALITY OF VOLTAGE STORING MEANS CONNECTED RESPECTIVELY TO SAID RECEIVING MEANS AND EACH ADAPTED TO MAINTAIN THE PEAK VOLTAGE OF ITS RECEIVED SIGNAL FOR A PERIOD OF TIME; (C) A PLURALITY OF VOLTAGE CCMPARATORS, ONE FOR EACH STORING MEANS AND CONNECTED RESPECTIVELY THERETO AND ARRANGED TO RESPOND WHEN THE VOLTAGE OF THE SIGNAL STORED IN THE ASSOCIATED STORING MEANS EXCEEDS A PREDETERMINED THRESHOLD VALVE; (D) PARITY CHECKING MEANS CONNECTED TO SAID VOLTAGE COMPARATORS AND ADAPTED TO PRODUCE A "PARITY GOOD" SIGNAL WHEN THERE IS A CORRECT NUMBER OF CODE BITS IN THE OUTPUTS OF SAID VOLTAGE COMPARATORS AND TO PRODUCE A "PARITY BAD" SIGNAL WHEN THERE IS AN INCORRECT NUMBER OF CODE BITS IN THE OUTPUTS OF SAID VOLTAGE COMPARATORS; (E) INDIVIDUAL OUTPUT MEANS, ONE FOR EACH OF SAID VOLTAGE COMPARATORS; (F) GATING MEANS BETWEEN SAID VOLTAGE COMPARATORS AND SAID OUTPUT MEANS AND CONNECTED TO SAID PARITY CHECKING MEANS FOR DELIVERING THE SIGNALS ON THE OUTPUTS OF SAID VOLTAGE COMPARATORS TO SAID OUTPUT MEANS IN RESPONSE TO A "PARITY GOOD" SIGNAL FROM SAID PARITY CHECKING MEANS; (G) MEANS CONNECTED TO SAID PARITY CHECKING MEANS AND RESPONSIVE TO A "PARITY BAD" SIGNAL THEREFROM FOR GRADUALLY REDUCING THE EFFECTIVE THRESHOLD VALUE OF SAID VOLTAGE COMPARATORS, AND (H) MEANS THEREAFTER RESPONSIVE TO A "PARITY GOOD" SIGNAL FROM SAID PARITY CHECKING MEANS FOR DISABLING SAID THRESHOLD-VALUE-REDUCING MEANS AND FOR ENABLING SAID GATING MEANS.

References Cited (Backward Citations)

CA561797A Cited
US3098994A Cited
US2991372A Cited
US3214700A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1972-02-25 1972-08-26 1973-02-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1976-02-25 1976-08-26 1977-02-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1980-02-25 1980-08-26 1981-02-25 $7700.00 Window Closed / Lapsed

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