Data-processing element

Claim 2

A data-processing machine arranged for the processing of data in accordance with instructions, comprising a plurality of elements for storing information words representative of said data and of said instructions, means for extracting information words from said elements, and processing means for processing said information words in accordance with said instructions, said processing means including a plurality of instruction registers for receiving at least two different instructions from said extracting means and control means responsive to contents of said registers for generating commands to effect the concurrent processing of said two different instructions.

Claim 3

The data-processing machine as claimed in claim 1 wherein said processing means further includes branching means for causing said machine to select a predetermined subroutine in response to an instruction, means for initiating the more probable of two possible subroutines that are contingent upon the result of a data-processing operation before that result is available, and inhibiting means responsive to said result when available to inhibit said more probable subroutine when said result responsive means indicates a predetermined data result.

Claim 4

A data-processing machine arranged for the processing of data in accordance with instructions, comprising a plurality of elements for storing information words representative of said data and of said instructions, means for extracting information words from said elements including means for concurrently obtaining two information words from said storage elements, means for preferentially obtaining one of said information words where access to the same storage element is being sought for both said information words, and processing means for processing said information words in accordance with said instructions, said processing means including control means for receiving at least two different instructions from said extracting means and effecting the concurrent processing of said two different instructions.

Claim 5

A data-processing machine arranged for the processing of data in accordance with instructions, comprising a plurality of elements for storing information words representative of said data and of said instructions, means for extracting information words from said elements including means for concurrently obtaining two information words from said storage elements, means for preferentially obtaining one of said information words where access to the same storage element is being sought for both said information words, and processing means for processing said information words in accordance with said instructions, said processing means including control means for receiving at least two different instructions from said extracting means and effecting the concurrent processing of said two different instructions.

Claim 6

A data-processing machine as claimed in claim 3 wherein said information words are a next instruction word and a data word at an address specified by an instruction word preceding said next instruction word and said data word is the word preferentially obtained by the means therefor.

Claim 7

A data-processing machine adapted to process signals representative of data in accordance with a program of instruction words comprising a plurality of storage devices for storing said data signals and said instruction words, arithmetic means for processing a data word in accordance with an instruction word, first and second instruction registers, and program control means for controlling the transfer of instruction words and data signals from said storage devices in accordance with said program to enable the processing of data words by said arithmetic means and to effect the concurrent execution of more than one of said instructions, said program control means including means for transferring a first instruction word from a said storage device to said first instruction register for decoding and processing and for transferring a second instruction word from a said storage device to said first instruction register for the initiation of its decoding and processing before the completion of the processing of said first instruction word, and means to transfer said first instruction word to said second instruction register at substantially the same time that said second instruction word is transferred to said first instruction register with the continued processing of said first instruction word being controlled from said second register.

Claim 8

A data-processing machine adapted to process signals representative of data in accordance with a program of instruction words comprising a plurality of storage devices for storing said data signals and said instruction words, arithmetic means for processing a data word in accordance with an instruction word, first and second instruction registers, and program control means for controlling the transfer of instruction words and data signals from said storage devices in accordance with said program to enable the processing of data words by said arithmetic means and to effect the concurrent execution of more than one of said instructions, said program control means including means for transferring a first instruction word from a said storage device to said first instruction register for decoding and processing and for transferring a second instruction word from a said storage device to said first instruction register for the initiation of its decoding and processing before the completion of the processing of said first instruction word, and means to transfer said first instruction word to said second instruction register at substantially the same time that said second instruction word is transferred to said first instruction register with the continued processing of said first instruction word being controlled from said second register.

Claim 9

A data-processing machine adapted to process signals representative of data in accordance with a program of instruction words comprising a plurality of storage devices for storing said data signals and said instruction words, arithmetic means for processing a data word in accordance with an instruction word, first and second instruction registers, program control means for controlling the transfer of instruction words and data signals from said storage devices in accordance with said program to enable the processing of data words by said arithmetic means and to effect the concurrent execution of more than one of said instructions, said program control means including means for transferring a first instruction word from a said storage device to said first instruction register for decoding and processing and for transferring a second instruction word from a said storage device to said first instruction register for the initiation of its decoding and processing before the completion of the processing of said first instruction word, and means to transfer said first instruction word to said second instruction register at substantially the same time that said second instruction word is transferred to said first instruction register with the continued processing of said first instruction word being controlled from said second register, branching means for causing said machine to select a predetermined program subroutine in response to an instruction, means for initiating the more probable of two possible subroutines that are contingent upon the result of a data-processing operation in said arithmetic means before that result is available, and inhibiting means responsive to said result when said result is available to inhibit further processing of said more probable subroutine by said program control means when said arithmetic means produces a predetermined data result and to initiate processing by said program control means of the less probable of said two possible subroutines.

Claim 10

A data-processing machine adapted to process signals representative of data in accordance with a program of instruction words comprising a plurality of storage devices for storing said data signals and said instruction words, arithmetic means for processing a data word in accordance with an instruction word, first and second instruction registers, program control means for controlling the transfer of instruction words and data signals from said storage devices in accordance with said program to enable the processing of data words by said arithmetic means and to effect the concurrent execution of more than one of said instructions, said program control means including means for transferring a first instruction word from a said storage device to said first instruction register for decoding and processing and for transferring a second instruction word from a said storage device to said first instruction register for the initiation of its decoding and processing before the completion of the processing of said first instruction word, and means to transfer said first instruction word to said second instruction register at substantially the same time that said second instruction word is transferred to said first instruction register with the continued processing of said first instruction word being controlled from said second register, branching means for causing said machine to select a predetermined program subroutine in response to an instruction, means for initiating the more probable of two possible subroutines that are contingent upon the result of a data-processing operation in said arithmetic means before that result is available, and inhibiting means responsive to said result when said result is available to inhibit further processing of said more probable subroutine by said program control means when said arithmetic means produces a predetermined data result and to initiate processing by said program control means of the less probable of said two possible subroutines.

Claim 11

The data-processing machine as claimed in claim 5 wherein said program control means includes means for sensing data and instruction requests, and means for preferentially obtaining a data word when access to the same storage device is being sought for a data word and an instruction word.

Claim 12

The data-processing machine as claimed in claim 5 and further including means for inhibiting the concurrent processing of said instructions.

Claim 13

The data-processing machine as claimed in claim 5 and further including branching means responsive to an instruction for causing said machine to branch to a subprogram of instructions, said branching means being responsive to a particular condition, means for initiating the processing of the more probable of two possible subroutines of instructions that may immediately follow said branch instruction before the existence of said condition is determined, and means responsive to said condition for optionally inhibiting the processing of said more probable subroutine of instructions.

Claim 14

The apparatus as claimed in claim 9 wherein said branching means includes means operative when said condition is determined to exist to inhibit selection of the next instruction in the more probable subroutine by said program control means and to transfer the address of the first instruction in the less probable subroutine to said program control means so that the first instruction in said less probable subroutine is read from a said storage device during the memory cycle immediately following the determination that the condition exists.

Claim 15

A data-processing machine arranged for the processing of data in accordance with instrUctions, comprising a plurality of elements for storing information words representative of said data and of said instructions, means for extracting information words from said elements including means for concurrently requesting instruction and data signals from said storage devices and means for sensing said data and instruction transfer requests, said sensing means permitting the reading of requested data signals from a storage device in preference to a requested instruction where the concurrently requested information words are both stored in the same storage device, and processing means for processing said information words in accordance with said instructions, said processing means including control means for receiving at least two different instructions from said extracting means and effecting the concurrent processing of said two different instructions.

Claim 16

A data-processing machine arranged for the processing of data in accordance with instrUctions, comprising a plurality of elements for storing information words representative of said data and of said instructions, means for extracting information words from said elements including means for concurrently requesting instruction and data signals from said storage devices and means for sensing said data and instruction transfer requests, said sensing means permitting the reading of requested data signals from a storage device in preference to a requested instruction where the concurrently requested information words are both stored in the same storage device, and processing means for processing said information words in accordance with said instructions, said processing means including control means for receiving at least two different instructions from said extracting means and effecting the concurrent processing of said two different instructions.

Claim 17

A data-processing machine adapted to process signals representative of data in accordance with instructions, said machine being operable in a sequence of instruction cycles which may be arranged as several programs of data-processing instructions and having means for cycling said machine in a first program of instructions, branching means responsive to an instruction of said first program for causing said machine to branch to a second program of said instructions if a certain condition exists including sensing means to determine if said condition exists, means for initiating the processing of a next instruction before said sensing means can determine if said condition exists, and means responsive to said sensing means for inhibiting the processing of said next instruction and initiating the processing of another instruction.

Claim 18

A data-processing machine adapted to process signals representative of data in accordance with instructions, said machine being operable in a sequence of instruction cycles which may be arranged as several programs of data-processing instructions and having means for cycling said machine in a first program of instructions, branching means responsive to an instruction of said first program for causing said machine to branch to a second program of said instructions if a certain condition exists including sensing means to determine if said condition exists, means for initiating the processing of a next instruction before said sensing means can determine if said condition exists, and means responsive to said sensing means for inhibiting the processing of said next instruction and initiating the processing of another instruction.

Claim 19

A data-processing machine as claimed in claim 12 wherein said next instruction is from said first program, said substitute instruction is from said second program, and it is more probable that said condition will not exist than that it will exist.

Claim 20

In a digital computer cyclically operative to process data signals in accordance with a program of instruction words, each instruction word including an instruction portion adapted to control the generation of commands and an address portion which may specify the address in a memory element of a data word operand to be manipulated in accordance with commands generated under the control of said instruction portion, having arithmetic means adapted to process data words in accordance with commands generated in response to said instruction portions, means for specifying the memory address of the next instruction to be executed by said computer, and means responsive to said address portion for specifying the memory address of the required data word operand, a plurality of memory elements for storing said data signals and said instruction words, and program control means including a plurality of instruction-decoding and command-generating means, each said instruction-decoding and command-generating means including a register for storing an instruction portion, means to concurrently reference said memory elements in accordance with said instruction specifying means and said data word specifying means and to read out instruction and data word signals from the referenced memory elements in parallel, means responsive to said memory reference means normally operative to transfer the instruction portion of a first instruction word read out from a first memory element to a first one of said instruction decoding means, and the data signals read out from a secondary memory element to said arithmetic means, said transfer means being subsequently operative to transfer the instruction portion of said first instruction word to a second one of said instruction decoding means, and to transfer a second instruction word specified by said instruction specifying means from one memory element to said first instruction-decoding means and to transfer the data word signals specified by said data word-specifying means from another memory element to said arIthmetic means for processing in accordance with the instruction portion of said first instruction word in said second instruction-decoding means to enable said data word signals to be processed in accordance with said first instruction for obtaining a data result while the processing of said second instruction is concurrently proceeding.

Claim 21

In a digital computer cyclically operative to process data signals in accordance with a program of instruction words, each instruction word including an instruction portion adapted to control the generation of commands and an address portion which may specify the address in a memory element of a data word operand to be manipulated in accordance with commands generated under the control of said instruction portion, having arithmetic means adapted to process data words in accordance with commands generated in response to said instruction portions, means for specifying the memory address of the next instruction to be executed by said computer, and means responsive to said address portion for specifying the memory address of the required data word operand, a plurality of memory elements for storing said data signals and said instruction words, and program control means including a plurality of instruction-decoding and command-generating means, each said instruction-decoding and command-generating means including a register for storing an instruction portion, means to concurrently reference said memory elements in accordance with said instruction specifying means and said data word specifying means and to read out instruction and data word signals from the referenced memory elements in parallel, means responsive to said memory reference means normally operative to transfer the instruction portion of a first instruction word read out from a first memory element to a first one of said instruction decoding means, and the data signals read out from a secondary memory element to said arithmetic means, said transfer means being subsequently operative to transfer the instruction portion of said first instruction word to a second one of said instruction decoding means, and to transfer a second instruction word specified by said instruction specifying means from one memory element to said first instruction-decoding means and to transfer the data word signals specified by said data word-specifying means from another memory element to said arIthmetic means for processing in accordance with the instruction portion of said first instruction word in said second instruction-decoding means to enable said data word signals to be processed in accordance with said first instruction for obtaining a data result while the processing of said second instruction is concurrently proceeding.

Claim 22

The apparatus as claimed in claim 14 wherein said program control means further includes means to inhibit memory reference by said instruction-specifying means during any memory cycle that said data word-specifying means and said instruction word-specifying means are referencing the same memory element.

Claim 23

The apparatus as claimed in claim 14 wherein said program control means further includes means optionally operative to inhibit the concurrent reference of memory elements by said instruction specifying means and said data word-specifying means.

Claim 24

A data-processing machine arranged for the processing of data in accordance with sequentially presented instructions comprising a memory means for storing digitally coded information words representative of said data and said instructions, arithmetic means adapted to process data words in accordance with said instructions, control means for receiving instruction words from said memory means and generating commands in response to said instruction words to effect the processing of data words by said arithmetic means, and means to transfer at the same time from said memory means a data word to said arithmetic means to be processed by one instruction word and a second instruction word to said control means, said second instruction word being transferred to said control means while said one instruction word is held in said control means.

Claim 25

A data-processing machine arranged for the processing of data in accordance with sequentially presented instructions comprising a memory means for storing digitally coded information words representative of said data and said instructions, arithmetic means adapted to process data words in accordance with said instructions, control means for receiving instruction words from said memory means and generating commands in response to said instruction words to effect the processing of data words by said arithmetic means, and means to transfer at the same time from said memory means a data word to said arithmetic means to be processed by one instruction word and a second instruction word to said control means, said second instruction word being transferred to said control means while said one instruction word is held in said control means.

Claim 26

In a digital computing system having storage means for retaining coded information applied thereto, first instruction-register means connected to receive from said storage means combinations of coded signals constituting an instruction message portion, and arithmetic means adapted to perform calculating operations in response to signals from said first register means corresponding to an instruction message portion stored therein, the combination therewith of control means including: second instruction-register means connected to receive instruction message portions from said storage means; selector means operative, in the presence of a first instruction message portion in said first register means and a second instruction message portion in said second register means, for identifying a third instruction message in said storage means in response to an address portion of said second instruction during performance of a calculating operation by said computer in response to an instruction message portion of said first instruction; and signal-responsive means operable by an execution signal from said computer indicative of the completion of a calculating operation for clearing said first register means of said first instruction message portion and thereafter initiating a transfer of said second instruction message portion from said second register means to said first register means and a transfer of an instruction portion of said third message to said second register means, thereby enabling said arithmetic means to operate on a portion of said second instruction message during transfer of said third instruction message and identification by said selector means of a further instruction message in said storage means.

Claim 27

In a digital computing system having storage means for retaining coded information applied thereto, first instruction-register means connected to receive from said storage means combinations of coded signals constituting an instruction message portion, and arithmetic means adapted to perform calculating operations in response to signals from said first register means corresponding to an instruction message portion stored therein, the combination therewith of control means including: second instruction-register means connected to receive instruction message portions from said storage means; selector means operative, in the presence of a first instruction message portion in said first register means and a second instruction message portion in said second register means, for identifying a third instruction message in said storage means in response to an address portion of said second instruction during performance of a calculating operation by said computer in response to an instruction message portion of said first instruction; and signal-responsive means operable by an execution signal from said computer indicative of the completion of a calculating operation for clearing said first register means of said first instruction message portion and thereafter initiating a transfer of said second instruction message portion from said second register means to said first register means and a transfer of an instruction portion of said third message to said second register means, thereby enabling said arithmetic means to operate on a portion of said second instruction message during transfer of said third instruction message and identification by said selector means of a further instruction message in said storage means.

Claim 28

A digital computer having a memory for storing instructions, control means including means for extracting instructions from the memory, first means for storing said instructions and performing steps in the manipulation thereof, second means for storing said instructions and performing steps in the manipulation thereof, means for transferring an instruction from said first means to said second means and means for transferring a further instruction to said means after said first named instruction haS been transferred to said second means, and while said first named instruction is stored in said second means.

Claim 29

A digital computer having a memory for storing instructions, control means including means for extracting instructions from the memory, first means for storing said instructions and performing steps in the manipulation thereof, second means for storing said instructions and performing steps in the manipulation thereof, means for transferring an instruction from said first means to said second means and means for transferring a further instruction to said means after said first named instruction haS been transferred to said second means, and while said first named instruction is stored in said second means.

Claim 30

A digital computer having arithmetic means, an addressable memory for storing instruction words and operand words, and a plurality of addressable registers for storing operand words, control means including sequencing means for extracting instruction words from said memory, a first instruction register coupled to said memory for storing instruction words extracted from said memory, a second instruction register to which instruction words are transferred from said first instruction register, means for extracting operand words from said memory and from said addressable registers as determined by the contents of an instruction word, and for transferring said operand words to said arithmetic means, an address register storing the address of an addressable register and means controlled from the instruction words stored in the first and second instruction registers and the address register effective to control the transfer of instruction words from the memory to said first instruction register, and from said first instruction register to said second instruction register so that a plurality of instruction words are manipulated concurrently.

Claim 31

A digital computer having arithmetic means, an addressable memory for storing instruction words and operand words, and a plurality of addressable registers for storing operand words, control means including sequencing means for extracting instruction words from said memory, a first instruction register coupled to said memory for storing instruction words extracted from said memory, a second instruction register to which instruction words are transferred from said first instruction register, means for extracting operand words from said memory and from said addressable registers as determined by the contents of an instruction word, and for transferring said operand words to said arithmetic means, an address register storing the address of an addressable register and means controlled from the instruction words stored in the first and second instruction registers and the address register effective to control the transfer of instruction words from the memory to said first instruction register, and from said first instruction register to said second instruction register so that a plurality of instruction words are manipulated concurrently.

Claim 32

A digital computer having a memory for storing instructions and operands, apparatus coupled to said memory for selecting operands and instructions, arithmetic means coupled to said memory to receive said operands, and control means coupled to said memory for receiving instructions and controlling said computer in response thereto having means for processing instructions in an overlapping sequence including a first register for storing a part of an instruction designating an address in said memory, a second register for storing a part of an instruction controlling the operation of said arithmetic means, a third register for storing a part of an instruction which controls said apparatus for the selection of operands and instructions, and means coupled to said registers and said memory for controlling the transfer of instructions to said registers whereby said registers store at least portions of different instructions so that different steps in the overall processing of a plurality of instructions may be carried out simultaneously.

Claim 33

A digital computer having a memory for storing instructions and operands, apparatus coupled to said memory for selecting operands and instructions, arithmetic means coupled to said memory to receive said operands, and control means coupled to said memory for receiving instructions and controlling said computer in response thereto having means for processing instructions in an overlapping sequence including a first register for storing a part of an instruction designating an address in said memory, a second register for storing a part of an instruction controlling the operation of said arithmetic means, a third register for storing a part of an instruction which controls said apparatus for the selection of operands and instructions, and means coupled to said registers and said memory for controlling the transfer of instructions to said registers whereby said registers store at least portions of different instructions so that different steps in the overall processing of a plurality of instructions may be carried out simultaneously.

Claim 34

A digital computer having a memory for storing instructions and operands, arithmetic means for the arithmetic processing of operands, and a plurality of instruction registers for storage of instructions, means effective to generate signals controlling the transfer of data between said memory and said instruction registers, and between said memory and said arithmetic means so that different steps in the processing of data from a plurality of instructions may be carried on simultaneously, means responsive to contingencies arising from the nature of the instruction to be processed and from accessibility of a memory, effective to suspend the transfer of data and responsive to termination of such contingencies for restoring said suspended transfer of data so that minimum interference occurs in the simultaneous processing of said different steps from said plurality of instructions.

Claim 35

A digital computer having a memory for storing instructions and operands, arithmetic means for the arithmetic processing of operands, and a plurality of instruction registers for storage of instructions, means effective to generate signals controlling the transfer of data between said memory and said instruction registers, and between said memory and said arithmetic means so that different steps in the processing of data from a plurality of instructions may be carried on simultaneously, means responsive to contingencies arising from the nature of the instruction to be processed and from accessibility of a memory, effective to suspend the transfer of data and responsive to termination of such contingencies for restoring said suspended transfer of data so that minimum interference occurs in the simultaneous processing of said different steps from said plurality of instructions.

Claim 36

A digital computer having a memory means for storing data comprising instructions and operands which memory means during a designated time period may or may not be accessible, means producing a signal indicating the accessibility of said memory means, means responsive to instructions for governing the operation of said computer comprising a plurality of registers for storage of instruction data whereby different steps in the processing of a plurality of instructions may be carried on by said computer simultaneously, sequencing means calling for the extraction of instruction data from said memory, and control means responsive to said signal effective to control the operation of said sequencing means and transfers of instruction data between said registers wherein said control means is maintained in a predEtermined condition by generation of a memory accessibility signal thereby to cause said sequencing means during said designated time period to extract new instruction data from said memory means.

Claim 37

A digital computer having a memory means for storing data comprising instructions and operands which memory means during a designated time period may or may not be accessible, means producing a signal indicating the accessibility of said memory means, means responsive to instructions for governing the operation of said computer comprising a plurality of registers for storage of instruction data whereby different steps in the processing of a plurality of instructions may be carried on by said computer simultaneously, sequencing means calling for the extraction of instruction data from said memory, and control means responsive to said signal effective to control the operation of said sequencing means and transfers of instruction data between said registers wherein said control means is maintained in a predEtermined condition by generation of a memory accessibility signal thereby to cause said sequencing means during said designated time period to extract new instruction data from said memory means.

Claim 38

A digital computer having a memory means for storing data comprising instructions and operands which memory means during designated time period may or may not be accessible for data transfers, means producing signals indicating the accessibility of said memory and means responsive to instructions for governing the operation of said computer comprising a plurality of registers for the storage of a plurality of instructions whereby different steps in the processing of a plurality of instructions may be carried on by said computer simultaneously, sequencing means calling for the extraction of instruction data from said memory means and control means effective to control the operation of said sequencing means, said control means including first means responsive to signals indicative of the accessibility of said memory for an instruction to develop an actuating signal for said sequencing means, and second means responsive to the condition of said first means so that on failure of a memory accessibility signal said second means remains in a predetermined condition and said sequencing means makes a repeated memory call for the same instruction.

Claim 39

A digital computer having a memory means for storing data comprising instructions and operands which memory means during designated time period may or may not be accessible for data transfers, means producing signals indicating the accessibility of said memory and means responsive to instructions for governing the operation of said computer comprising a plurality of registers for the storage of a plurality of instructions whereby different steps in the processing of a plurality of instructions may be carried on by said computer simultaneously, sequencing means calling for the extraction of instruction data from said memory means and control means effective to control the operation of said sequencing means, said control means including first means responsive to signals indicative of the accessibility of said memory for an instruction to develop an actuating signal for said sequencing means, and second means responsive to the condition of said first means so that on failure of a memory accessibility signal said second means remains in a predetermined condition and said sequencing means makes a repeated memory call for the same instruction.

Claim 40

A digital computer having a memory for storing instructions, means for extracting a sequence of instructions from said memory, a plurality of instruction registers coupled to said memory for receiving and storing said sequence of instructions wherein at least two of said instruction registers store different instructions, means coupled to said at least two instruction registers for manipulating a plurality of instructions concurrently, instruction execution means controlled by an instruction from one of said instruction registers for executing said instruction, and control means for causing said instruction execution means to be controlled by a different instruction from said instruction registers after said execution means has responded to the instruction last controlling it.

Claim 41

A digital computer having a memory for storing instructions, means for extracting a sequence of instructions from said memory, a plurality of instruction registers coupled to said memory for receiving and storing said sequence of instructions wherein at least two of said instruction registers store different instructions, means coupled to said at least two instruction registers for manipulating a plurality of instructions concurrently, instruction execution means controlled by an instruction from one of said instruction registers for executing said instruction, and control means for causing said instruction execution means to be controlled by a different instruction from said instruction registers after said execution means has responded to the instruction last controlling it.

Claim 42

The computer defined in claim 25 wherein said means for extracting instructions is governed by said control means to extract a new instruction from said memory for transfer to said instruction registers after said instruction execution means has responded to the instruction last controlling it.

Claim 43

A digital computer having arithmetic means for performing computations, an addressable memory having a plurality of locations for storing instructions and operands, said instructions comprising a portion designating an operation to be performed by said computer and at least one address portion indicative of an address in said memory, control means for extracting instructions from said memory, a plurality of instruction registers for receiving instructions from said memory including at least a first instruction register coupled to said memory for storing instructions extracted from said memory, a second instruction register coupled to said first instruction register for receiving instructions from said first instruction register, an address register adapted to receive a portion of an instruction specifying an address in said memory and means controlled by at least one portion of an instruction stored in one of said first and second instruction registers and the address stored in said address register effective to control the transfer of instructions from the memory to said first instruction register, and from said first instruction register to said second instruction register so that a plurality of instructions are being manipulated concurrently.

Claim 44

A digital computer having arithmetic means for performing computations, an addressable memory having a plurality of locations for storing instructions and operands, said instructions comprising a portion designating an operation to be performed by said computer and at least one address portion indicative of an address in said memory, control means for extracting instructions from said memory, a plurality of instruction registers for receiving instructions from said memory including at least a first instruction register coupled to said memory for storing instructions extracted from said memory, a second instruction register coupled to said first instruction register for receiving instructions from said first instruction register, an address register adapted to receive a portion of an instruction specifying an address in said memory and means controlled by at least one portion of an instruction stored in one of said first and second instruction registers and the address stored in said address register effective to control the transfer of instructions from the memory to said first instruction register, and from said first instruction register to said second instruction register so that a plurality of instructions are being manipulated concurrently.

Claim 45

A digital computer having arithmetic means for performing computations, an addressable memory having a plurality of locations for storing instructions and operands; said instructions comprising a portion designating an operation to be performed by said computer and at least one address portion indicativE of an address in said memory, control means including sequencing means for extracting instructions from said memory in a sequence, a plurality of instruction registers for receiving instructions from said memory including at least a first instruction register coupled to said memory for storing instructions extracted from said memory, a second instruction register coupled to said memory for storing instructions extracted from said memory, an address register adapted to receive a portion of an instruction specifying an address in said memory and means controlled by at least one portion of an instruction stored in one of said first and second instruction registers and the address stored in said address register effective to control the transfer of instructions from the memory to said first instruction register and to said second instruction register so that a plurality of instructions are being manipulated concurrently.

Claim 46

A digital computer having arithmetic means for performing computations, an addressable memory having a plurality of locations for storing instructions and operands; said instructions comprising a portion designating an operation to be performed by said computer and at least one address portion indicativE of an address in said memory, control means including sequencing means for extracting instructions from said memory in a sequence, a plurality of instruction registers for receiving instructions from said memory including at least a first instruction register coupled to said memory for storing instructions extracted from said memory, a second instruction register coupled to said memory for storing instructions extracted from said memory, an address register adapted to receive a portion of an instruction specifying an address in said memory and means controlled by at least one portion of an instruction stored in one of said first and second instruction registers and the address stored in said address register effective to control the transfer of instructions from the memory to said first instruction register and to said second instruction register so that a plurality of instructions are being manipulated concurrently.

Claim 47

A digital computer comprising an addressable memory having a plurality of locations for storing instructions, said instructions comprising a portion designating an operation to be performed by said computer and at least one address portion indicative of an address in said memory, control means for addressing said memory to extract instructions from said memory, a plurality of instruction registers for receiving instructions from said memory, means adapted for receiving from said memory an address portion of an instruction word and for addressing said memory in response thereto, means operative to produce a signal when a conflict may occur in concurrently addressing said memory from said control means and said receiving means, and means responsive to the output of said signalling means to control the transfer of instructions from said memory to said instruction registers.

Claim 48

A digital computer comprising an addressable memory having a plurality of locations for storing instructions, said instructions comprising a portion designating an operation to be performed by said computer and at least one address portion indicative of an address in said memory, control means for addressing said memory to extract instructions from said memory, a plurality of instruction registers for receiving instructions from said memory, means adapted for receiving from said memory an address portion of an instruction word and for addressing said memory in response thereto, means operative to produce a signal when a conflict may occur in concurrently addressing said memory from said control means and said receiving means, and means responsive to the output of said signalling means to control the transfer of instructions from said memory to said instruction registers.

Claim 49

A digital computer comprising an addressable memory having a plurality of locations for storing instructions and operands, said instructions comprising a portion designating an operation to be performed by said computer and at least one address portion indicative of an address in said memory, control means for addressing said memory to extract instructions from said memory in a sequence, first and second instruction registers for receiving instructions from said memory, means coupled to said instruction registers for processing a plurality of instructions concurrently, means adapted for receiving from said memory an address portion of an instruction word and for addressing said memory in response thereto, signaling means operative to produce an output when said memory is successfully addressed by either said control means or said receiving means, and means controlled by the output of said signaling means effective to control the transfer of instructions from the memory to said first instruction register, and from said first instruction register to said second instruction register so that a plurality of instructions are being manipulated concurrently.

Claim 50

A digital computer comprising an addressable memory having a plurality of locations for storing instructions and operands, said instructions comprising a portion designating an operation to be performed by said computer and at least one address portion indicative of an address in said memory, control means for addressing said memory to extract instructions from said memory in a sequence, first and second instruction registers for receiving instructions from said memory, means coupled to said instruction registers for processing a plurality of instructions concurrently, means adapted for receiving from said memory an address portion of an instruction word and for addressing said memory in response thereto, signaling means operative to produce an output when said memory is successfully addressed by either said control means or said receiving means, and means controlled by the output of said signaling means effective to control the transfer of instructions from the memory to said first instruction register, and from said first instruction register to said second instruction register so that a plurality of instructions are being manipulated concurrently.

Claim 51

A digital computer having memory means for storing instructions and operands, sequencing means, arithmetic means and at least first and second instruction registers for storing instructions, cycling means comprising means effective to actuate said sequencing means to extract first and second instructions from said memory means, means effective to control the modification of a portion of said first instruction and transfer another portion of said first instruction to said second instruction register, and means controlled from one of said instruction registers to extract operands as required from the memory means and to initiate execution of said first instruction by said arithmetic means, said cycling means actuating said sequencing means and controlling the transfer of instructions between said instruction registers so that a further instruction is called from said memory while said first and second instructions are still undergoing processing.

Claim 52

A digital computer having memory means for storing instructions and operands, sequencing means, arithmetic means and at least first and second instruction registers for storing instructions, cycling means comprising means effective to actuate said sequencing means to extract first and second instructions from said memory means, means effective to control the modification of a portion of said first instruction and transfer another portion of said first instruction to said second instruction register, and means controlled from one of said instruction registers to extract operands as required from the memory means and to initiate execution of said first instruction by said arithmetic means, said cycling means actuating said sequencing means and controlling the transfer of instructions between said instruction registers so that a further instruction is called from said memory while said first and second instructions are still undergoing processing.

Claim 53

A digital computer having data-processing means, control means for coNtrolling the operation of said data-processing means according to an instruction and an addressable memory means for storing data comprising instructions and operands which memory means during a designated time period may or may not be accessible, said memory means including means responsive to the addressing thereof for indicating the availability of said memory means, said control means comprising a plurality of instruction registers coupled together and to said memory means for controlling the operation of said computer and storing a plurality of different instructions, each of said instruction registers controlling portions of said computer so that different steps in the processing of said plurality of instructions may be carried on simultaneously, sequencing means calling for the extraction of instructions from said memory means in a sequence for transfer to said instruction registers, and cycling means responsive to signals indicative of the accessibility of said memory means and effective to control the operation of said sequencing means and the transfer of instructions between said instruction registers wherein said cycling means is maintained in a predetermined condition by generation of a signal indicating accessibility of said memory means to cause said sequencing means each during each said designated time period to extract new instruction data from said memory means for transfer to said instruction registers.

Claim 54

A digital computer having data-processing means, control means for coNtrolling the operation of said data-processing means according to an instruction and an addressable memory means for storing data comprising instructions and operands which memory means during a designated time period may or may not be accessible, said memory means including means responsive to the addressing thereof for indicating the availability of said memory means, said control means comprising a plurality of instruction registers coupled together and to said memory means for controlling the operation of said computer and storing a plurality of different instructions, each of said instruction registers controlling portions of said computer so that different steps in the processing of said plurality of instructions may be carried on simultaneously, sequencing means calling for the extraction of instructions from said memory means in a sequence for transfer to said instruction registers, and cycling means responsive to signals indicative of the accessibility of said memory means and effective to control the operation of said sequencing means and the transfer of instructions between said instruction registers wherein said cycling means is maintained in a predetermined condition by generation of a signal indicating accessibility of said memory means to cause said sequencing means each during each said designated time period to extract new instruction data from said memory means for transfer to said instruction registers.

Claim 55

A digital computer having a memory for storing instructions, control means including means for extracting information from the memory, first means for storing said instructions and for automatically performing first steps in the manipulation thereof, second means for storing said instructions and performing second steps in the manipulation thereof, means for transferring an instruction from said first means to said second means and means for transferring a further instruction to said first means after said first named instruction has been transferred to said second means and while said first named instruction is stored in said second means.

Claim 56

A digital computer having a memory for storing instructions, control means including means for extracting information from the memory, first means for storing said instructions and for automatically performing first steps in the manipulation thereof, second means for storing said instructions and performing second steps in the manipulation thereof, means for transferring an instruction from said first means to said second means and means for transferring a further instruction to said first means after said first named instruction has been transferred to said second means and while said first named instruction is stored in said second means.

Claim 57

A data-processing machine adapted to process signals representative of instructions having means for storing said instructions, means for processing said instructions including a plurality of instruction registers for receiving at least two different instructions and control means responsive to contents of said registers for effecting the concurrent processing of said two different instructions, means for selecting and extracting instructions successively from said storage means for processing by said processing means, sensing means for determining if a certain condition exists during the processing of a first instruction, and means responsive to said sensing means for inhibiting the processing of a second instruction extracted subsequently to said first instruction and for causing a third instruction to be extracted and processed instead of said second instruction.

Claim 58

A data-processing machine adapted to process signals representative of instructions having means for storing said instructions, means for processing said instructions including a plurality of instruction registers for receiving at least two different instructions and control means responsive to contents of said registers for effecting the concurrent processing of said two different instructions, means for selecting and extracting instructions successively from said storage means for processing by said processing means, sensing means for determining if a certain condition exists during the processing of a first instruction, and means responsive to said sensing means for inhibiting the processing of a second instruction extracted subsequently to said first instruction and for causing a third instruction to be extracted and processed instead of said second instruction.