Patent US3737637A successfully refreshed from Google Patents.
US3737637A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data generator
Assignee: International Business Machines Corp
•
Filing: 1971-12-13
•
Granted: 1973-06-05
•
Expires: 1991-12-13
Abstract
Abstract Variable delay circuits generate output signals representing test signals having controlled timing widths. The output signals are generated by the variable delay circuits in accordance with data received from a memory under the control of a program of instructions stored in the memory. A fixed cycle clock initiates accessing of instructions one at a time. Each instruction in turn identifies control data which is supplied at times specified by a variable cycle clock. The delay circuits are assigned delay amounts and selected at times calculated to modify signals at their input desired amounts. The delay circuits are selected individually and in combination to give a wide variety of delay amounts. If desired, external input signals may be passed through the data generator with or without modification or may be stored in the memory for subsequent use in generating output signals. Signals resulting from these various operations may be freely interspersed. The output signals may be supplied directly to test a connected system or to an intermediate storage device such as magnetic tape which may subsequently be used to test the connected system.
Inventors
- 👤 R Frankeny
- 👤 J Tuttle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 04:58
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/30
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
70 words
In an apparatus for supplying degraded signals useful for testing a signal-responsive unit: a source for supplying a plurality of normally timed signals within the normal operating range of the tested unit; and variable delay means, connected between said source and said tested unit, operable to progressively and selectively delay predetermined ones of said plurality of timed signals until they are outside the normal operating range of the tested unit.
Claim 2
Dependent Claim
70 words
In an apparatus for supplying degraded signals useful for testing a signal-responsive unit: a source for supplying a plurality of normally timed signals within the normal operating range of the tested unit; and variable delay means, connected between said source and said tested unit, operable to progressively and selectively delay predetermined ones of said plurality of timed signals until they are outside the normal operating range of the tested unit.
Claim 3
Dependent Claim
33 words
The apparatus of claim 1, wherein the source of said timed signals is a selected one of an external source of a plurality of normally timed signals and a single internal signal generator.
Claim 4
Dependent Claim
23 words
The apparatus of claim 2, wherein the single internal signal generator comprises an oscillator and control means for modifying signals from the oscillator.
Claim 5
Dependent Claim
102 words
A data generator for generating degraded data for a tested unit, including: a source of normal input signals; variable delay circuits having an input connected to said source and an output, and operable in accordance with specified delay values to delay normal input signals to form at the output degraded output signals; delay register means, connected to said variable delay circuits, for specifying delay values in accordance with supplied delay value signals divided into a plurality of range sections, the sections manifesting progressively smaller ranges of delay values; and supply means, connected to said delay register means, for supplying delay value signals.
Claim 6
Dependent Claim
102 words
A data generator for generating degraded data for a tested unit, including: a source of normal input signals; variable delay circuits having an input connected to said source and an output, and operable in accordance with specified delay values to delay normal input signals to form at the output degraded output signals; delay register means, connected to said variable delay circuits, for specifying delay values in accordance with supplied delay value signals divided into a plurality of range sections, the sections manifesting progressively smaller ranges of delay values; and supply means, connected to said delay register means, for supplying delay value signals.
Claim 7
Dependent Claim
23 words
The generator of claim 4, wherein the means for supplying delay value signals include a storage means containing manifestations indicative of delay values.
Claim 8
Dependent Claim
29 words
The generator of claim 5, wherein the manifestations in said storage are arranged in a sequence and there is provided a counter for accessing said manifestations in said sequence.
Claim 9
Dependent Claim
30 words
The generator of claim 6, wherein there are further provided counting and comparing means operable in cooperation with said storage means to permit repeated use of the same delay values.
Claim 10
Dependent Claim
85 words
A combination for supplying a plurality of time variable output signals, comprising: a source of clocking signals; a plurality of delay registers operable to store delay value signals; a plurality of variable delay circuits, connected to said clocking signals source and to said delay registers, operable to delay the clocking signals in accordance with said delay value signals; and a data storage means, connectable to said variable delay circuits and registers, operable to supply delay values to said registers and to identify particular delay circuits.
Claim 11
Dependent Claim
85 words
A combination for supplying a plurality of time variable output signals, comprising: a source of clocking signals; a plurality of delay registers operable to store delay value signals; a plurality of variable delay circuits, connected to said clocking signals source and to said delay registers, operable to delay the clocking signals in accordance with said delay value signals; and a data storage means, connectable to said variable delay circuits and registers, operable to supply delay values to said registers and to identify particular delay circuits.
Claim 12
Dependent Claim
61 words
The combination of claim 8, wherein there are additionally provided: gating means for interconnecting the delay circuits; an interconnection register, associated with said gating means, for storing signals indicative of interconnections to be made by said gating means; and means for supplying from said data storage means to said interconnection register signals identifying particular delay circuits which are to be interconnected.
Claim 13
Dependent Claim
32 words
The combination of claim 9, wherein there are provided: control means, associated with said data storage means and said interconnection register, for blocking specified interconnections in accordance with signals from said storage.
Claim 14
Dependent Claim
133 words
A source of timed signals for testing an electronic device, including: a store capable of storing information, accessible as signals, characterized as instructions, each instruction having two fields; variable signal modifying means, connected with said store and having data and control inputs and data outputs, operable to modify as signals at its data output data input signals received at its data inputs in accordance with information received at its control inputs from said store; instruction decoding means, connected to said store, operable to interpret information received from said store; and control means, connected to said instruction decoding means and said variable signal modifying means, operable to supply information from one field of instructionS in said store to said variable signal modifying means control unit in accordance with interpretation information from the other field.
Claim 15
Dependent Claim
133 words
A source of timed signals for testing an electronic device, including: a store capable of storing information, accessible as signals, characterized as instructions, each instruction having two fields; variable signal modifying means, connected with said store and having data and control inputs and data outputs, operable to modify as signals at its data output data input signals received at its data inputs in accordance with information received at its control inputs from said store; instruction decoding means, connected to said store, operable to interpret information received from said store; and control means, connected to said instruction decoding means and said variable signal modifying means, operable to supply information from one field of instructionS in said store to said variable signal modifying means control unit in accordance with interpretation information from the other field.
Claim 16
Independent Claim
57 words
A method comprising: supplying clocking signals; storing delay value signals in delay registers; supplying delay values to said registers identifying particular delay circuits; delaying the clocking signals in accordance with said delay value signals; storing signals indicative of interconnections to be made between delay circuits; and supplying signals identifying particular delay circuits which are to be interconnected.
Claim 17
Independent Claim
57 words
A method comprising: supplying clocking signals; storing delay value signals in delay registers; supplying delay values to said registers identifying particular delay circuits; delaying the clocking signals in accordance with said delay value signals; storing signals indicative of interconnections to be made between delay circuits; and supplying signals identifying particular delay circuits which are to be interconnected.
Claim 18
Dependent Claim
18 words
The method of claim 12, including the further step of: blocking specified interconnections in accordance with blocking signals.
Claim 19
Independent Claim
70 words
A method for testing an electronic device, including the steps of: entering in a store signals, characterized as instructions, each instruction having two fields; modifying in a signal modifier data input signals in accordance with control information from said store; interpreting information received from said store; and supplying information from one field of instructions in said store to said signal modifier in accordance with interpretation information from the other field.
Claim 20
Independent Claim
70 words
A method for testing an electronic device, including the steps of: entering in a store signals, characterized as instructions, each instruction having two fields; modifying in a signal modifier data input signals in accordance with control information from said store; interpreting information received from said store; and supplying information from one field of instructions in said store to said signal modifier in accordance with interpretation information from the other field.
References Cited (Backward Citations)
US3633174A
Cited
US3675133A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-04 | 1976-12-04 | 1977-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-04 | 1980-12-04 | 1981-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-04 | 1984-12-04 | 1985-06-05 | $7700.00 | Window Closed / Lapsed |