← Back to Patent Explorer
US3633174A Expired / Lapsed US ⏱️ 0.0 years remaining

Memory system having self-adjusting strobe timing

Assignee: United States Department of the Navy
•
Filing: 1970-04-14
•
Granted: 1972-01-04
•
Expires: 1990-04-14
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An adaptive memory system comprising a core memory, utilizing externally generated read strobe pulses; an exerciser which writes a test pattern into the memory, and compares the result with a predetermined desired performance of the memory; a strobe generator which controls the exerciser and the memory system, performs a failure analysis on the results of the testing by the exerciser and determines the optimum timing of the read strobe pulses supplied to the memory; and interface gating, used to tie the memory to equipment outside the memory system during its normal mode of operation, or to the exerciser during its adaptive mode of operation.

Inventors

  • 👤 Jon H Griffin

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 10:42
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G11C29/028; G11C11/00; G11C11/02; G11C11/06; G11C11/06007; G11C29/04; G11C29/50; G11C29/50012

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 309 words
An adaptive memory system that provides self adjusting strobe pulse timing comprising: a memory having data inputs and outputs, being adapted to accommodate externally generated strobe pulses; interface gating connected to said memory by the data inputs and outputs of said memory and connected to data lines external to said memory system; an exerciser connected to said interface gating and being capable, upon actuation, of causing said interface gating to switch the data inputs and outputs of said memory from connection to the data lines external to said memory system to connection to said exerciser and thereupon performing a series of failure tests on said memory; a strobe generator connected to said memory and said exerciser for generating strobe pulses timed as required by said memory in response to said strobe generator''s analysis of information received from said exerciser which is based on the failure tests said exerciser performed, and for actuating said exerciser, upon command, to initiate and perform the series of failure tests on said memory, said strobe generator comprising: a failure analysis means for receiving failure test information from said exerciser and determining the optimum strobe pulse timing based on the received information; a delay line having a plurality of taps along its length, each of the taps being connected through a switching means to a common point, the connection of each tap causing a different strobe pulse timing; and logic circuit means responsive to the performance of each test in the series of failure tests performed by said exerciser for switching the connection to said common point from one tap to another tap along said delay line and responsive to the connection of the last tap of the plurality of taps to said common point for switching the connection to the tap causing the optimum strobe pulse timing as determined by said failure analysis means.
Claim 2
Dependent Claim 309 words
An adaptive memory system that provides self adjusting strobe pulse timing comprising: a memory having data inputs and outputs, being adapted to accommodate externally generated strobe pulses; interface gating connected to said memory by the data inputs and outputs of said memory and connected to data lines external to said memory system; an exerciser connected to said interface gating and being capable, upon actuation, of causing said interface gating to switch the data inputs and outputs of said memory from connection to the data lines external to said memory system to connection to said exerciser and thereupon performing a series of failure tests on said memory; a strobe generator connected to said memory and said exerciser for generating strobe pulses timed as required by said memory in response to said strobe generator''s analysis of information received from said exerciser which is based on the failure tests said exerciser performed, and for actuating said exerciser, upon command, to initiate and perform the series of failure tests on said memory, said strobe generator comprising: a failure analysis means for receiving failure test information from said exerciser and determining the optimum strobe pulse timing based on the received information; a delay line having a plurality of taps along its length, each of the taps being connected through a switching means to a common point, the connection of each tap causing a different strobe pulse timing; and logic circuit means responsive to the performance of each test in the series of failure tests performed by said exerciser for switching the connection to said common point from one tap to another tap along said delay line and responsive to the connection of the last tap of the plurality of taps to said common point for switching the connection to the tap causing the optimum strobe pulse timing as determined by said failure analysis means.
Claim 3
Dependent Claim 74 words
The adaptive memory system of claim 1 wherein said failure analysis means comprises: a machine capable of assuming four different states, and producing logic zero and logic one outputs, the state assumed depending on the state said machine is in when an input signal, either a failure or no-failure signal, is received; a serial register for receiving the outputs of said machine which outputs taken together determine the best estimate of strobe pulse timing.
Claim 4
Dependent Claim 146 words
The adaptive memory system of claim 2 wherein said logic circuit means comprises: a plurality of AND gates, equal in number to the plurality of taps on said delay line, each tap on said delay line connected to a respective input of a different one of said plurality of AND gates; a plurality of NOT gates, equal in number to said plurality of AND gates, the outputs of said plurality of NOT gates less one each being connected to a respective input of a different one of said plurality of AND gates, the remaining one of said plurality of NOT gates having all the outputs of said plurality of AND gates connected to its input; a serial register having a plurality of outputs equal to said plurality of NOT gates less one, each output being connected to a respective input of said plurality of NOT gates.
Claim 5
Dependent Claim 146 words
The adaptive memory system of claim 1 wherein said logic circuit means comprises: a plurality of AND gates, equal in number to the plurality of taps on said delay line, each tap on said delay line connected to a respective input of a different one of said plurality of AND gates; a plurality of NOT gates, equal in number to said plurality of AND gates, the outputs of said plurality of NOT gates less one each being connected to a respective input of a different one of said plurality of AND gates, the remaining one of said plurality of NOT gates having all the outputs of said plurality of AND gates connected to its input; a serial register having a plurality of outputs equal to said plurality of NOT gates less one, each output being connected to a respective input of said plurality of NOT gates.

References Cited (Backward Citations)

US3208050A Cited
US3363235A Cited
US3478286A Cited
US3440609A Cited
US3394355A Cited
US3537075A Cited
US3501754A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-01-03 1975-07-05 1976-01-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-01-03 1979-07-05 1980-01-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-01-03 1983-07-05 1984-01-04 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag