Dual clock memory access control

Claim 2

A digital computer system comprising a digital processor operating in synchronism with clock pulses at a first frequency, a plurality of input/output units operating in synchronism with clock pulses at a second frequency that is at least half said first frequency, clock pulse generating means for generating clock pulses at said first and second frequencies, the clock pulse generating means being coupled to the processor and to the input/output units, an addressable memory having a memory cycle time for transferring a unit of digital information into or out of a specified address location substantially equal to the period of the second frequency clock pulses, means in each of the input/output units for initiating an access request signal when the respective units are ready to transfer a unit of digital information between the memory and the respective input/output unit, means sending an access granted signal to the processor on alternate ones of the second frequency clock pulse periods, and priority means responsive to said access request signals for sending an access granted signal to any one of the input/output units or the processor on a predetermined priority basis on intermediate ones of the second frequency clock pulse periods.

Claim 3

A digital computer system comprising a digital processor operating in synchronism with clock pulses at a first frequency, a plurality of input/output units operating in synchronism with clock pulses at a second frequency that is at least half said first frequency, clock pulse generating means for generating clock pulses at said first and second frequencies, the clock pulse generating means being coupled to the processor and to the input/output units, an addressable memory having a memory cycle time for transferring a unit of digital information into or out of a specified address location substantially equal to the period of the second frequency clock pulses, means in each of the input/output units for initiating an access request signal when the respective units are ready to transfer a unit of digital information between the memory and the respective input/output unit, means sending an access granted signal to the processor on alternate ones of the second frequency clock pulse periods, and priority means responsive to said access request signals for sending an access granted signal to any one of the input/output units or the processor on a predetermined priority basis on intermediate ones of the second frequency clock pulse periods.

Claim 4

A digital computer system comprising a digital processor operating in synchronism with clock pulses at a first frequency, a plurality of input/output units operating in synchronism with clock pulses at a second frequency that is at least half said first frequency, clock pulse generating means for generating clock pulses at said first and second frequencies, the clock pulse generating means being coupled to the processor and to the input/output units, an addressable memory having a memory cycle time for transferring a unit of digital information into or out of a specified address location substantially equal to the period of the second frequency clock pulses, means in each of the input/output units for initiating an access request signal when the respective units are ready to transfer a unit of digital information between the memory and the respective input/output unit, means sending an access granted signal to the processor on alternate ones of the second frequency clock pulse periods, and priority means responsive to said access request signals for sending an access granted signal to any one of the input/output units or the processor on a predetermined priority basis on intermediate ones of the second frequency clock pulse periods.

Claim 5

Apparatus as defined in claim 1 further including a buffer register, means responsive to an input/output unit when granted access to main memory for transferring an address associated with the particular input/output unit into the buffer register during one of said alternate clock periods when the processor is granted access to the main memory, the address being transferred from the buffer register, and means for initIating a main memory access to the particular input/output during the next period of the second clock pulse generating means.

Claim 6

Apparatus as defined in claim 2 further including first and second address memories, the first address memory storing addresses associated with the processor and the second address memory storing addresses associated with each of the input/output units, means in the processor for reading out an address from the first address memory to the main memory during an access to main memory by the processor, means in each of the input/output units for reading out an associated address from the second address memory to the buffer register during one of said alternate clock periods which the processor is granted access to the main memory.

Claim 7

Apparatus of claim 3 wherein the main memory includes an address register associated with the main memory, and further including means directly coupling the address register to the first address memory means during a main memory access initiated by the processor, and means directly coupling the buffer register to the address register during a main memory access initiated by one of the input/output units.

Claim 8

A digital computer comprising a processor operating at a first clock frequency, at least one input/output control unit operating at a second clock frequency substantially slower than the first clock frequency, a main memory, control means connected to the processor and main memory for transferring data between the processor and main memory at the clock frequency of the processor, control means connected to the input/output control unit and main memory for transferring data between the input/outut control unit and main memory at the clock frequency of the input/output control unit, the processor and input/output control unit including means generating an access to memory request signal when a transfer of data is needed, means responsive to a request signal from only the processor for granting access to memory by the processor during each clock period at the second clock frequency, and means responsive to request signals from the processor and at least an input/output unit at the same time for granting access to memory alternately by the processor and the requesting input/output unit during successive clock periods at the second clock frequency.

Claim 9

A digital computer comprising a processor operating at a first clock frequency, at least one input/output control unit operating at a second clock frequency substantially slower than the first clock frequency, a main memory, control means connected to the processor and main memory for transferring data between the processor and main memory at the clock frequency of the processor, control means connected to the input/output control unit and main memory for transferring data between the input/outut control unit and main memory at the clock frequency of the input/output control unit, the processor and input/output control unit including means generating an access to memory request signal when a transfer of data is needed, means responsive to a request signal from only the processor for granting access to memory by the processor during each clock period at the second clock frequency, and means responsive to request signals from the processor and at least an input/output unit at the same time for granting access to memory alternately by the processor and the requesting input/output unit during successive clock periods at the second clock frequency.

Claim 10

A computer system comprising a processor operating at a first clock frequency, at least one input/output unit operating at a second clock frequency at least half the first clock frequency, main memory, first and second address storage units for storing addresses pointing to locations in the main memory associated respectively with the processor and with each of the input/output units, means responsive to an access request signal from the processor for addressing the memory from the first address storage unit and initiating a transfer between the processor and the memory location specified by the address storage unit, the first address storage means being controlled and addressed from the processor at the first clock frequency, the second storage means being controlled and addressed from the requesting input/output units at the second clock frequency, means responsive to an access request from an input/output control unit for addressing the memory from the second address storage unit and initiating a transfer between the input/output control unit and the memory location specified by the address storage unit, said last named means including a buffer register between the second address unit and the main memory for temporarily storing an address from the second address storage.

Claim 11

A computer system comprising a processor operating at a first clock frequency, at least one input/output unit operating at a second clock frequency at least half the first clock frequency, main memory, first and second address storage units for storing addresses pointing to locations in the main memory associated respectively with the processor and with each of the input/output units, means responsive to an access request signal from the processor for addressing the memory from the first address storage unit and initiating a transfer between the processor and the memory location specified by the address storage unit, the first address storage means being controlled and addressed from the processor at the first clock frequency, the second storage means being controlled and addressed from the requesting input/output units at the second clock frequency, means responsive to an access request from an input/output control unit for addressing the memory from the second address storage unit and initiating a transfer between the input/output control unit and the memory location specified by the address storage unit, said last named means including a buffer register between the second address unit and the main memory for temporarily storing an address from the second address storage.