Timing circuit for providing linear timing periods

Abstract

Abstract An electronic timing circuit for generating linear timing periods by providing a constant current discharge path from a storage capacitor. A storage capacitor is charged through a gating transistor to a preset level. The gating transistor is then turned off, and the capacitor discharges through the serial arrangement of a field-effect transistor and a resistor. The field-effect transistor is self-biased such that the current flow from the capacitor through the transistor to the resistor is constant with respect to time. This is accomplished by varying the impedance of the transistor proportionately to the charge on the storage capacitor. The potential at the junction of the field-effect transistor and the resistor is detected by a high input impedance device which drives an output circuit. A delay on deenergization mode of operation is provided wherein a steady state current is continuously passed through the serial arrangement of the field-effect transistor and the resistor. When the output circuit is to be deenergized, the steady state current is turned off allowing the storage capacitor to discharge for a linear period of time at the end of which the output is deenergized. The duration of the discharge or timing interval may be adjusted by varying the bias at the gate of the FET.

Inventors

• 👤 Favre E Eaton

Bibliographic Details