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US3582678A
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Pulse interval measurement apparatus
Assignee: SP-MICROWAVE Inc
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Filing: 1969-08-06
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Granted: 1971-06-01
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Expires: 1989-08-06
Abstract
Abstract First and second transistor switching pairs are connected to receive first and second pulses respectively. Each switching pair is biased to respond only when the instantaneous value of the appropriate pulse exceeds a predetermined threshold. A capacitor is charged through a constant current network from the time that the first switching pair is actuated until the time that the second switching pair is actuated so that the magnitude of the charge on the capacitor represents the time interval between pulses. Individual halves of a dual FET are connected in hold and discharge circuits across the capacitor.
Inventors
- 👤 David C Davis Jr
- 👤 Carl T Nations
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:21
CPC Classifications
G; G04; G04F; G04F10/00; G04F10/10; H; H03; H03K; H03K9/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
153 words
Apparatus for measuring the time delay between consecutive pulses comprising a storage capacitor; charging means to charge said capacitor at a substantially linear rate throughout a charging interval; first and second switching means coupled to said charging means to initiate and terminate a charging interval, respectively; a first field effect transistor connected across said storage capacitor and biased to be normally conducting; means in said first switching means to drive said first field effect transistor into the cutoff condition for a predetermined period commencing with the initiation of the charging interval; an output terminal; a holding circuit, said holding circuit including a second field effect transistor having its gate electrode connected to a terminal on said capacitor and its source electrode connected to said output terminal; and means in said holding circuit to bias said second field effect transistor so that its gate and source electrodes are at essentially the same voltage level.
Claim 2
Dependent Claim
153 words
Apparatus for measuring the time delay between consecutive pulses comprising a storage capacitor; charging means to charge said capacitor at a substantially linear rate throughout a charging interval; first and second switching means coupled to said charging means to initiate and terminate a charging interval, respectively; a first field effect transistor connected across said storage capacitor and biased to be normally conducting; means in said first switching means to drive said first field effect transistor into the cutoff condition for a predetermined period commencing with the initiation of the charging interval; an output terminal; a holding circuit, said holding circuit including a second field effect transistor having its gate electrode connected to a terminal on said capacitor and its source electrode connected to said output terminal; and means in said holding circuit to bias said second field effect transistor so that its gate and source electrodes are at essentially the same voltage level.
Claim 3
Dependent Claim
36 words
The apparatus of claim 1 in which said first and second switching means each includes a transistor switching pair biased to remain in the quiescent state until actuated by a stimulus or response input pulse respectively.
Claim 4
Dependent Claim
35 words
The apparatus of claim 2 in which each of the switching pairs is biased so that the instantaneous amplitude of an input pulse will reach the same predetermined value before a transistor pair is actuated.
Claim 5
Dependent Claim
99 words
The apparatus of claim 3 in which each switching pair includes first and second transistors, said first transistor in each pair being connected to receive the input signals applied to that pair; means to provide a forward biasing signal; each of said second transistors being normally biased to the same conductivity level by said forward biasing signal; each of said first transistors being biased to cutoff by the current flowing through the second transistor in the same pair so that any input signal must reach the same specified instantaneous amplitude before the corresponding first transistor actuates that switching pair.
Claim 6
Dependent Claim
86 words
The apparatus of claim 1 further characterized in that said first field effect transistor has a drain electrode, a source electrode, and a gate electrode; said drain electrode being connected to one terminal of said capacitor; said source electrode being connected to the other terminal of said capacitor; said apparatus being further characterized in that said means to drive the first field effect transistor into the cutoff condition is a one-shot multivibrator having its output connected to the gate electrode of said first field effect transistor.
Claim 7
Dependent Claim
62 words
The apparatus of claim 4 in which the gate electrode of said second field effect transistor is connected to the same capacitor terminal as the drain electrode of the first field effect transistor, and in which the means to bias said second field effect transistor is an adjustable constant current source connecTed to the source electrode of said second field effect transistor.
Claim 8
Dependent Claim
87 words
The apparatus of claim 5 in which said adjustable constant current source includes a third field effect transistor having a drain electrode connected to said output terminal, a gate electrode connected directly to a source of negative voltage and a source electrode coupled to said source of negative voltage through a variable resistor, said variable resistor having a resistance suitable to adjust the current through said third field effect transistor to a value sufficient to equalize the gate and source voltages on said second field effect transistor.
Claim 9
Dependent Claim
62 words
The apparatus of claim 1 wherein each of said switching means includes first and second transistors arranged as a switching pair in which conduction in either one of said transistors drives the other transistor to cutoff, said switching pair being further proportioned so that the maximum current through either transistor is limited to a value below the saturation value for that transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |