Input/output channel

Claim 2

An input/output channel for providing a path for the transfer of information directly between a plurality of input/output attachments and a central processing unit and through the central processing unit to a main storage, said central processing unit being capable of operating on data from said attachments, said channel comprising, a first means for transmitting data from said attachments to said central processing unit, a second means for transmitting data from said central processing unit to said attachments, said first means including a first translator, for altering the data from said attachments to a form recognizable by said central processing unit, said second means including a second translator for altering the data from said central processing unit to a form recognizable by said attachments, and first and second logic means associated respectively with said first and second transmitting means for selectively causing data passing through the channel to either pass through said translators or bypass said translators if the data does not need to be translated.

Claim 3

A channel as claimed in claim 1 further including; means for receiving time-dependent requests from said attachments for use of said central processing unit, means for determining which of said attachments requesting the use of said central processing unit has the highest priority among a preassigned set of time-dependent priorities, and means, for granting use of said central processing unit to the one of said plurality of attachments requesting said use which has the highest priority of the requesting attachments.

Claim 4

An input/output channel for providing a path for the transfer of information between a plurality of input/output attachments, and a central processing unit and a main storage, wherein said central processing unit includes a plurality of registers, a portion of said registers being address registers for said attachments, comprising; selection means under the control of said attachments for selecting in response to a selection signal from an attachment granted a cycle steal the one of said address registers corresponding to the attachment granted a cycle steal by the central processing unit, there being preassigned to each attachment one of said address registers, said selection signal being used to identify one of said address registers, said selection means including checking means for checking that only one address register is selected and for disabling said selection means if more than one register is selected.

Claim 5

An input/output channel for providing a path for the transfer of information between a plurality of input/output attachments, and a central processing unit and a main storage, wherein said central processing unit includes a plurality of registers, a portion of said registers being address registers for said attachments, comprising; selection means under the control of said attachments for selecting in response to a selection signal from an attachment granted a cycle steal the one of said address registers corresponding to the attachment granted a cycle steal by the central processing unit, there being preassigned to each attachment one of said address registers, said selection signal being used to identify one of said address registers, said selection means including checking means for checking that only one address register is selected and for disabling said selection means if more than one register is selected.

Claim 6

A channel as claimed in claim 3 further including interrupt means, for requesting an interrupt cycle from said central processing unit on command of an attachment, said interrupt means including interrupt priority logic means for passing to said address registers only the one interrupt request which is the highest among a preassigned hierarchy of priorities.

Claim 7

An input/output channel providing a path for the transfer of information directly between a plurality of input/output attachments and a central processing unit and through the central processing unit to a main storage, said central processing unit including at least one group of registers, said channel comprising; means for carrying information from said attachments to said central processing unit, means for carrying information from said central processing unit to said attachments, a plurality of cycle steal request lines, each line being assignable to a plurality of attachments, time dependent priority means for controlling the order, according to a preassigned hierarchy, in which said attachments are granted central processing unit produced cycle steals, a single request thereby being assignable to a pLurality of attachments, and means including said means for carrying information from said central processing unit for indicating to said attachments the one attachment granted a cycle steal.

Claim 8

An input/output channel providing a path for the transfer of information directly between a plurality of input/output attachments and a central processing unit and through the central processing unit to a main storage, said central processing unit including at least one group of registers, said channel comprising; means for carrying information from said attachments to said central processing unit, means for carrying information from said central processing unit to said attachments, a plurality of cycle steal request lines, each line being assignable to a plurality of attachments, time dependent priority means for controlling the order, according to a preassigned hierarchy, in which said attachments are granted central processing unit produced cycle steals, a single request thereby being assignable to a pLurality of attachments, and means including said means for carrying information from said central processing unit for indicating to said attachments the one attachment granted a cycle steal.

Claim 9

A channel as claimed in claim 5 further including; selection means under the control of said attachment for selecting a preassigned one of said group of registers in said unit, said preassigned register having been preassigned to the attachment granted a cycle steal, in response to a selection signal from the attachment granted a cycle steal, said selection means including a means for checking that only one of said group of registers is selected at a time.

Claim 10

A channel as claimed in claim 6 wherein; said means for transmitting information from said attachments includes first translator means for making the information transferred from said attachments compatible with said central processing unit, and said means for transmitting information from said central processing unit includes second translator means for making the information transferred from said central processing unit compatible with said attachments.

Claim 11

A channel as claimed in claim 7 further including interrupt means for controlling the selection of one of said group of registers in response to a plurality of interrupt requests from said attachments, said selection being based upon a preassigned hierarchy of priorities.

Claim 12

An input/output channel providing a path for the transfer of information between a plurality of input/output attachments and a central processing unit and through the central processing unit to a main storage, wherein said unit includes a group of local store registers and has the capability of granting a cycle steal comprising; a first means for transferring information from said attachments to said unit, said first means including, first translator means for translating data into a code recognizable by said central processing unit, and first logic means for selectively causing data to bypass said first translator means, second means for providing a path for the transfer of data from said unit to said attachments, said second means including second translator means for translating data into a code recognizable by said attachments, and second logic means for selectively causing data to bypass said second translator means, request means for selectively granting a cycle steal to one of a plurality of attachments simultaneously requesting a cycle steal, said selective granting being on the basis of a time dependent preassigned priority, means, coupled between said request means and said second means, for transferring to said second means a signal identifying the attachment granted a cycle steal, selection means, under the control of the attachments, for selecting one of said local store registers in said central processing unit, said register containing an address in said storage wherein is stored an instruction or data required by one of said attachments, said selection means further including checking means for checking that a single register is selected at any point in time and for indicating when more than one register is selected, and interrupt means, responsive to interrupt requests from said attachments for granting an interrupt cycle to only one of said attachments in accordance with a preassigned priority.

Claim 13

An input/output channel providing a path for the transfer of information between a plurality of input/output attachments and a central processing unit and through the central processing unit to a main storage, wherein said unit includes a group of local store registers and has the capability of granting a cycle steal comprising; a first means for transferring information from said attachments to said unit, said first means including, first translator means for translating data into a code recognizable by said central processing unit, and first logic means for selectively causing data to bypass said first translator means, second means for providing a path for the transfer of data from said unit to said attachments, said second means including second translator means for translating data into a code recognizable by said attachments, and second logic means for selectively causing data to bypass said second translator means, request means for selectively granting a cycle steal to one of a plurality of attachments simultaneously requesting a cycle steal, said selective granting being on the basis of a time dependent preassigned priority, means, coupled between said request means and said second means, for transferring to said second means a signal identifying the attachment granted a cycle steal, selection means, under the control of the attachments, for selecting one of said local store registers in said central processing unit, said register containing an address in said storage wherein is stored an instruction or data required by one of said attachments, said selection means further including checking means for checking that a single register is selected at any point in time and for indicating when more than one register is selected, and interrupt means, responsive to interrupt requests from said attachments for granting an interrupt cycle to only one of said attachments in accordance with a preassigned priority.

Claim 14

The input/output channel as claimed in claim 11 wherein said attachments are arranged in a plurality of groups each attachment in a group being coupled to said channel through a common bank of lines, said channel further including a plurality of SELECT buses each associated with a different bank of lines, said selection means being comprised of a plurality of SELECT logic circuits one associated with each SELECT bus and means responsive to the output of said SELECT logic circuits for disabling the selection means when more than one of said SELECT logic circuits designates a local store register.