Test apparatus for digital computer

Claim 2

In a computer system in which a data processor is operable for executing a program to transmit data words to and receive data words from memory locations in an addressable memory, apparatus for monitoring a data word in any selected memory location for changes made by the processor, said apparatus comprising means including an interval timer for repeatedly reading out the data word from the same selected location in memory at timed intervals controlled by said interval timer, means storing the data word initially read out of memory from said selected location by the reading out means, means comparing the data word from the same memory location each time it is subsequently read out of memory from said location with the data word in said storing means, and means responsive to the comparing means for signaling whenever the data word read out is not equal to the data word in said storing means.

Claim 3

Apparatus as defined in claim 1 further including means responsive to said comparing means for halting the operation of the data processor whenever the data word read out of memory is not equal to the word in the storing means.

Claim 4

Apparatus as defined in claim 1, further comprising means including a mask register for limiting comparison by the comparison means to preselected portions of the data words being compared by the comparing means.

Claim 5

Apparatus for testing the contents of a storage location in the main memory of a digital computer comprising register means for storing the address of a selected location in memory, a first storage register, means responsive to the address in the address register for initially reading out the contents of the addressed location in memory into the first register, a second register, timing means, means responsive to the contents of the address register and the timing means for periodically reading out the contents of the addressed location in memory into the second register at time intervals controlled by said timing means, comparing means coupled to the first and second registers for providing an output signal that signals when the contents of the two registers are not identical, and control means responsive to the output signal from the comparing means for halting the operation of said means reading out the contents of the addressed location in memory into the second register and indicating that the contents of the two registers are not identical.

Claim 6

Apparatus for testing the contents of a storage location in the main memory of a digital computer comprising register means for storing the address of a selected location in memory, a first storage register, means responsive to the address in the address register for initially reading out the contents of the addressed location in memory into the first register, a second register, timing means, means responsive to the contents of the address register and the timing means for periodically reading out the contents of the addressed location in memory into the second register at time intervals controlled by said timing means, comparing means coupled to the first and second registers for providing an output signal that signals when the contents of the two registers are not identical, and control means responsive to the output signal from the comparing means for halting the operation of said means reading out the contents of the addressed location in memory into the second register and indicating that the contents of the two registers are not identical.

Claim 7

Apparatus as defined in claim 4 further including a mask register for indicating which portions of the contents of the two registers are to be compared, and means controlled by the mask register for limiting the portions of the contents of the first and second registers coupled to the compare means.

Claim 8

In a data processing system having an addressable memory, apparatus for monitoring any selected address location in the memory to determine when data stored at the location is changed, comprising an address register, first and second data registers, comparison means coupled to the first and second registers, the comparison means providing an output signal for indicating when the data in the first and second registers are not equal, first means for initiating the transfer of data stored in memory from the address location in memory specified by the address register to the first data register, second means including a variable settable interval timer for initiating the transfer of data repeatedly, at intervals fixed by the setting of said interval timer, from the same address location in memory specified by the address register to the second data register, means activating the first means and second means in sequence, and means responsive to the signal from the comparison means for terminating the repetitive operation of the seconD means when the comparison means output signal indicates the contents of the first and second registers are not equal.

Claim 9

In a data processing system having an addressable memory, apparatus for monitoring any selected address location in the memory to determine when data stored at the location is changed, comprising an address register, first and second data registers, comparison means coupled to the first and second registers, the comparison means providing an output signal for indicating when the data in the first and second registers are not equal, first means for initiating the transfer of data stored in memory from the address location in memory specified by the address register to the first data register, second means including a variable settable interval timer for initiating the transfer of data repeatedly, at intervals fixed by the setting of said interval timer, from the same address location in memory specified by the address register to the second data register, means activating the first means and second means in sequence, and means responsive to the signal from the comparison means for terminating the repetitive operation of the seconD means when the comparison means output signal indicates the contents of the first and second registers are not equal.