Patent US3597682A successfully refreshed from Google Patents.
US3597682A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable testing unit for single shot testing
Assignee: E H RESEARCH LAB Inc
•
Filing: 1968-11-12
•
Granted: 1971-08-03
•
Expires: 1988-11-12
Abstract
Abstract A programmable testing system for testing large scale array integrated circuits and similar devices having several inputs and outputs. The device is coupled from an input standpoint to two pulse generators and several DC power supplies and from an output standpoint to a single-shot strobing voltmeter and a single-shotswitching time converter. The pulse generators, DC power supplies, switching time converter, and single-shot strobing voltmeter are programmed by individually coupled and separate program registers preloaded with instructions from a core memory. A system control unit controls the filling or loading of these program registers. The program registers also control a switching matrix to couple the device under test and their terminals to the proper inputs and outputs. The control unit senses when the test sequence is over and when the entire test on the device is completed. This provides for a completely automatic testing sequence. When one testing sequence ends and another is to begin only those program registers whose parameters are changed are reloaded thus saving essential time in the testing procedure and effectively utilizing the single-shot capability of the testing instruments.
Inventors
- 👤 John C Hubbs
- 👤 Thomas E Castanera
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:52
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31926; G01R31/31903; G01R31/31908; G06; G06F; G06F1/00; G06F1/02; G06F1/03
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
167 words
A programmable testing system for a device under test having a plurality of inputs and outputs, comprising: memory means for storing testing instructions, pulse generating means for providing testing pulses, a plurality of test instruments responsive to a single output pulse from said device for providing test information, a plurality of program registers coupled to said memory means for controlling a plurality of functions in accordance with said testing instructions, said functions including selected registers routing outputs of said device to said test instruments, and including other selected registers for routing testing pulses from said pulse generating means to the inputs of said device to cause outputs of said device to provide said output pulses, and control means for loading said registers with said testing instructions from said memory for one test sequence, for sensing when said test sequence is finished and updating only those program registers where the last test sequence is to be modified and for sensing the completion of the testing on said device.
Claim 2
Dependent Claim
167 words
A programmable testing system for a device under test having a plurality of inputs and outputs, comprising: memory means for storing testing instructions, pulse generating means for providing testing pulses, a plurality of test instruments responsive to a single output pulse from said device for providing test information, a plurality of program registers coupled to said memory means for controlling a plurality of functions in accordance with said testing instructions, said functions including selected registers routing outputs of said device to said test instruments, and including other selected registers for routing testing pulses from said pulse generating means to the inputs of said device to cause outputs of said device to provide said output pulses, and control means for loading said registers with said testing instructions from said memory for one test sequence, for sensing when said test sequence is finished and updating only those program registers where the last test sequence is to be modified and for sensing the completion of the testing on said device.
Claim 3
Dependent Claim
167 words
A testing system as in claim 1 where one of said selected instruments is a switching time converter for measuring the time interval between two discrete points on a single output pulse from said device under test, the first point in time being determined by a start voltage threshold level and the second point by a stop voltage threshold level, another of said selected instruments being a strobing voltmeter for detecting the amplitude of an output pulse from said device under test at a predetermined time interval after a reference time, together with normalizing means including storage register means responsive to at least two magnitude measurements of an output pulse at two different points in time for storing said magnitudes, said switching time converter being responsive to a normalization indication of one of said program registers along with start and stop threshold information contained in such program register to recognize such start and stop threshold information as percentage values with reference to said two stored magnitude measurements.
Claim 4
Dependent Claim
240 words
A testing system as in claim 1 where one of said selected instruments is a switching time converter for measuring the time interval between two discrete points on a single output pulse from said device under test, the first point in time being determined by a start voltage threshold level and the second point by a stop voltage threshold level, together with differential measuring means including a forward-reverse counter said switching time converter being responsive to programmed directions from a program register for measuring a time interval, t1, from a predetermined reference voltage of an output pulse from said device under test to a predetermined low voltage point, relative to said reference voltage, of the next output pulse in time, said counter counting in a forward mode during all of said time interval, t1, said switching time converter also being responsive to said programmed directions for measuring a time interval, t2, between said reference voltage point on such next output pulse and a predetermined high voltage point, relative to said reference voltage, on the next subsequent output pulse, said counter being responsive to an indication in a program register for counting in a reverse mode from the start of said t2 time interval to zero count, said counter thereafter being conditioned to count forward until the end of t2, whereby the count contained in said counter is a measure of the time interval between said low and high voltage points.
References Cited (Backward Citations)
US3423677A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-02 | 1975-02-01 | 1975-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-02 | 1979-02-01 | 1979-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-02 | 1983-02-01 | 1983-08-03 | $7700.00 | Window Closed / Lapsed |