Programmable counting circuit

Claim 2

A programmable counting circuit comprising: a multistage counting circuit; a truncation register; the truncation register having predetermined information bits therein identifying at least two discrete groups of stages within the counting circuit; a reset register; the reset register having predetermined information values stored therein and associated with respective ones of the discrete groups of stages; means for periodically incrementing information values stored in the multistage counting circuit; and means responsive to the contents of the multistage counting circuit, the contents of the truncation register and the contents of the reset register for detecting matches between the contents of the discrete groups of stages and their associated information values and for resetting any group of stages for which a match is detected.

Claim 3

A programmable counting circuit according to claim 1 further comprising means for programmatically altering the contents of the truncation register and of the reset register.

Claim 4

A programmable counting circuit comprising: a counting circuit having a plurality of stages; means for periodically incrementing information values stored in the counting circuit; a truncation register; the truncation register having bit locations associated with respective ones of the stages and predetermined information bits therein identifying at least one discrete group of stages within the counting circuit; a reset register; the reset register having bit locations associated with respective ones of the stages and predeterminEd information bits therein; means for comparing each stage of the counting circuit with its associated bit location in the reset register and for determining matches therebetween; means for generating a first signal associated with the highest order stage for which a match occurs with its associated bit location in the reset register and for which matches between all lower order stages and their associated bit locations in the reset register occur; means for generating a second signal when a first signal is generated with respect to a stage having a truncation information bit associated therewith; and means responsive to the second signal for resetting all stages of the discrete group of stages identified by the last mentioned truncation information bit.

Claim 5

A programmable counting circuit comprising: a counting circuit having a plurality of stages; means for periodically incrementing information values stored in the counting circuit; a truncation register; the truncation register having bit locations associated with respective ones of the stages and predetermined information bits therein identifying at least one discrete group of stages within the counting circuit; a reset register; the reset register having bit locations associated with respective ones of the stages and predeterminEd information bits therein; means for comparing each stage of the counting circuit with its associated bit location in the reset register and for determining matches therebetween; means for generating a first signal associated with the highest order stage for which a match occurs with its associated bit location in the reset register and for which matches between all lower order stages and their associated bit locations in the reset register occur; means for generating a second signal when a first signal is generated with respect to a stage having a truncation information bit associated therewith; and means responsive to the second signal for resetting all stages of the discrete group of stages identified by the last mentioned truncation information bit.

Claim 6

A programmable counting circuit according to claim 3 in which the means for generating a first signal comprises a plurality of logic means associated with respective ones of the stages, each logic means generating a first signal with respect to its associated stage only in response to the determination of a match with respect both to its associated stage and all prior stages.

Claim 7

A programmable counting circuit according to claim 4 in which the comparing means in response to the determination of each match presents a signal to the logic means associated with the stage for which a match is determined and presents signals to the logic means of all higher order stages.

Claim 8

A programmable counting circuit according to claim 5 in which the logic means are connected in parallel.

Claim 9

A programmable counting circuit according to claim 4 in which the logic means are connected in series.

Claim 10

A programmable counting circuit according to claim 4 in which the logic means are connected in series-parallel.

Claim 11

A programmable counting circuit according to claim 3 in which the resetting means comprises a plurality of logic means associated with respective ones of the stages, each logic means presenting a reset signal on an associated reset line in response to a second signal generated with respect to its associated stage or in response to a second signal generated with respect to any higher order stage.

Claim 12

A programmable counting circuit according to claim 9 in which the means for generating a second signal presents the second signal to the logic means associated with the stage having a truncation information bit associated therewith and to all of the logic means associated with lower order stages.

Claim 13

A programmable counting circuit according to claim 10 in which the logic means are connected in parallel.

Claim 14

A programmable counting circuit according to claim 9 in which each logic means presents a reset signal on its associated reset line in response to a signal presented on the reset line of any logic means associated with a higher order stage.

Claim 15

A programmable counting circuit according to claim 12 in which the logic means are connected in series.

Claim 16

A programmable counting circuit according to claim 9 in which the logic means are connected in series-parallel.

Claim 17

A programmable signal generating circuit comprising: a multistage counting circuit; means for periodically incrementing information values stored in the counting circuit; the counting circuit generating signals indicative of the information values stored therein; a multistage truncation register, each stage being associated with a respective stage of the counting circuit, the truncation register having a plurality of truncation bits stored therein, the bits identifying a plurality of truncated groups of stages within the counting circuit; a multistage reset register, each stage also being associated with a respective stage of the counting circuit and having predetermined information values stored therein; means for comparing each stage of the counting circuit with the associated stage of the reset register and for determining matches therebetween; means for generating a ''''forwaRd carry'''' signal with respect to the highest order stage for which a match occurs with its associated bit location in the reset register and for which matches between all lower order stages and their associated bit locations in the reset register occur; means responsive to the ''''forward carry'''' signal and to the contents of the truncation register for generating a ''''reverse carry'''' signal with respect to any stage comprising the highest order stage of a truncated group of stages and with respect to which a ''''forward carry'''' signal is generated; and means responsive to the ''''reverse carry'''' signal for resetting its associated stage and all lower order stages of the counting circuit.

Claim 18

A programmable signal generating circuit comprising: a multistage counting circuit; means for periodically incrementing information values stored in the counting circuit; the counting circuit generating signals indicative of the information values stored therein; a multistage truncation register, each stage being associated with a respective stage of the counting circuit, the truncation register having a plurality of truncation bits stored therein, the bits identifying a plurality of truncated groups of stages within the counting circuit; a multistage reset register, each stage also being associated with a respective stage of the counting circuit and having predetermined information values stored therein; means for comparing each stage of the counting circuit with the associated stage of the reset register and for determining matches therebetween; means for generating a ''''forwaRd carry'''' signal with respect to the highest order stage for which a match occurs with its associated bit location in the reset register and for which matches between all lower order stages and their associated bit locations in the reset register occur; means responsive to the ''''forward carry'''' signal and to the contents of the truncation register for generating a ''''reverse carry'''' signal with respect to any stage comprising the highest order stage of a truncated group of stages and with respect to which a ''''forward carry'''' signal is generated; and means responsive to the ''''reverse carry'''' signal for resetting its associated stage and all lower order stages of the counting circuit.

Claim 19

A programmable signal generating circuit comprising: a multistage counting circuit; means for periodically incrementing information values stored in the counting circuit; the counting circuit generating signals indicative of the information stored therein; a single multistage register having at least one more stage then the counting circuit, an information bit in a selected stage therein manifesting the highest order stage of a single truncated group of stages within the counting circuit and an information value associated with this group of stages; means for comparing the information value stored in the truncated group of stages of the counting circuit with the information value stored in the register and for detecting a match therebetween; and means responsive to detection of a match and to the information bit in the selected stage of said register for resetting only the stages of the single truncated group of stages within the counting circuit independent of the information value in the stages of the counting circuit not within the truncated group.

Claim 20

A programmable signal generating circuit comprising: a multistage counting circuit; means for periodically incrementing information values stored in the counting circuit; the counting circuit generating signals indicative of the information stored therein; a single multistage register having at least one more stage then the counting circuit, an information bit in a selected stage therein manifesting the highest order stage of a single truncated group of stages within the counting circuit and an information value associated with this group of stages; means for comparing the information value stored in the truncated group of stages of the counting circuit with the information value stored in the register and for detecting a match therebetween; and means responsive to detection of a match and to the information bit in the selected stage of said register for resetting only the stages of the single truncated group of stages within the counting circuit independent of the information value in the stages of the counting circuit not within the truncated group.

Claim 21

A programmable signal generating circuit according to claim 16 in which the multistage counting circuit has ''''n'''' stages and the register has ''''n+1'''' bit locations, the first ''''n'''' bit locations being associated with respective ones of the ''''n'''' stages.

Claim 22

A programmable signal generating means according to claim 17 in which the comparing means comprises means for detecting the highest order bit location within the register in which a particular binary value is stored.