US6069814A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple input buffers for address bits
Assignee: Texas Instruments Inc
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Filing: 1995-01-10
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Granted: 2000-05-30
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Expires: 2015-01-10
Abstract
Abstract An input architecture for supply a plurality of signals to a plurality of circuit blocks located in an interior of an integrated circuit device. A plurality of unbuffered signal lines are each connected between a bondpad area and all of a plurality of input buffers. The input buffers are located adjacent to and connected to the plurality of circuit blocks instead of being located at the periphey of the integrated circuit adjacent the bondpad area.
Inventors
- 👤 James H. Liou
- 👤 Theodore W. Houston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:45
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/02; G11C5/025; G11C8/00; G11C8/06
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
75 words
An input architecture for supplying a plurality of signals to a plurality of circuit blocks located in an interior portion of an integrated circuit device, comprising: a bondpad area; a plurality of input buffers each located adjacent to and connected to one of said plurality of circuit blocks; a plurality of unbuffered signal lines, each of said plurality of unbuffered signal lines connected between said bondpad area and all of said plurality of input buffers.
Claim 2
Dependent Claim
75 words
An input architecture for supplying a plurality of signals to a plurality of circuit blocks located in an interior portion of an integrated circuit device, comprising: a bondpad area; a plurality of input buffers each located adjacent to and connected to one of said plurality of circuit blocks; a plurality of unbuffered signal lines, each of said plurality of unbuffered signal lines connected between said bondpad area and all of said plurality of input buffers.
Claim 3
Dependent Claim
15 words
The input architecture of claim 1, wherein said plurality of circuit blocks comprise memory blocks.
Claim 4
Dependent Claim
19 words
The input architecture of claim 1, wherein said plurality of circuit blocks are decode circuits for a memory array.
Claim 5
Dependent Claim
15 words
The input architecture of claim 1, wherein said unbuffered signal lines are unbuffered address lines.
Claim 6
Dependent Claim
91 words
A memory device comprising: a bondpad area; a memory array divided into a plurality of memory blocks; a decode circuit for each of said memory blocks, each of said decode circuits located adjacent an associated one of said memory blocks; a plurality of input buffers, each of said plurality of input buffers located proximate to and connected to one of said decode circuits; a plurality of unbuffered address lines, each of said plurality of unbuffered address lines being connected between said bondpad area and each of said plurality of input buffers.
Claim 7
Dependent Claim
91 words
A memory device comprising: a bondpad area; a memory array divided into a plurality of memory blocks; a decode circuit for each of said memory blocks, each of said decode circuits located adjacent an associated one of said memory blocks; a plurality of input buffers, each of said plurality of input buffers located proximate to and connected to one of said decode circuits; a plurality of unbuffered address lines, each of said plurality of unbuffered address lines being connected between said bondpad area and each of said plurality of input buffers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-30 | 2003-11-29 | 2004-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-30 | 2007-11-29 | 2008-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-30 | 2011-11-29 | 2012-05-30 | $7700.00 | Window Closed / Lapsed |