Redundancy scheme for a dynamic RAM

Claim 2

In a RAM having a plurality of main rows and colunmns of memory cells, a redundancy scheme for repairing defects in one or more of the main rows and columns of cells, comprising: a pluarlity of address buffers each receiving an input bit associated with a row address and an input bit associated with a column address of a main memory cell for sequentially developing output data representing the row address and output data representing the column address; a store associated with each address buffer for storing the row address of a defective main memory cell; a store associated with each address buffer for storing the column address of a defective main memory cell; comparison means associated with each address store for comparing row address data in said stores against row address data from said buffer, and for comparing column address data in said stores against column address data from said buffer so as to develop a binary control signal having a first state indicative of a match between compared data and a second state indicative of a mismatch between compared data; a plurality of spare memory cells; and spare selection means responsive to the control signal being in its first state for substituting a spare cell for the defective cell, whereby a single address buffer is time shared by the row and column address stores and by the comparison means.

Claim 3

A redundancy scheme as set forth in claim 1 wherein said spare memory cells are defined by a first plurality of spare rows of cells for replacing a first plurality of main rows of cells, a second plurality of spare rows of cells for replacing a second plurality of main rows of cells, and a plurality of spare columns of cells for replacing a defective column of main cells anywhere in the RAM.

Claim 4

A redundancy scheme as set forth in claim 2 wherein said row address store includes first and second row fuse circuits each adapted to store addresses of different rows having defective cells, wherein said column address store includes first and second column fuse circuits each adapted to store addresses of different columns having defective cells, wherein said comparison means includes a first comparator associated with said first row and column fuse circuits and a second comparator associated with said second row and column fuse circuits, means for coupling output data from the address buffer to each comparator, and switch means for coupling the output of each row fuse circuit to the comparators when the data output from the address buffer comprises row addresses and for coupling the output of each column fuse circuit to the comparators when the data output of the address buffer comprises column addresses.

Claim 5

A redundancy scheme as set forth in claim 1 wherein said spare memory cells are defined by a plurality of groups of spare rows of memory cells, each such group including four spare rows, and a plurality of groups of spare columns of memory cells, each of the latter groups including a plurality of spare columns and wherein said spare selection means is adapted to substitute a plurality of groups of spare rows and columns for main rows and columns having defective cells therein so as to repair relatively large defects which may impair adjacent main rows and columns of cells.

Claim 6

A redundancy scheme as set forth in claim 1 wherein said row address store includes a row fuse circuit comprising: a fuse having one end thereof coupled to a positive voltage supply; a fuse blowing transistor coupled between ground and the other end of the fuse and adapted to receive, during probe test, a signal which turns said transistor on for conducting fuse-blowing current to ground through said fuse; fuse and fuse output leads adapted to carry logic signals to said comparison means to indicate the status of said fuse; and fuse sensing circuitry coupled between said other end of the fuse and said output leads and adapted to be clocked for applying, to said output leads, logic levels indicative of the state of the fuse.

Claim 7

A redundancy scheme as set forth in claim 5 wherein said fuse sensing circuitry includes: means for precharging said output leads to high logic levels; a first transistor having its drain coupled to said other end of the fuse and adapted to receive a first clock signal at its gate; a second transistor having its drain coupled to the source of said first transistor and having a grounded source; a third transistor having its gate coupled to said other end of the fuse, having a source adapted to receive a second clock signal, and having a drain coupled to the gate of said second transistor; means for selectively coupling said other end of the fuse to said fuse output lead; and means for selectively coupling the drain of said third transistor to said fuse output lead, said first clock signal being selected to go from a low level to a high level and said second clock signal being adapted to go from a high level to a low level a relatively short time after said first clock signal goes to a high level so that, when the fuse is blown, said third transistor is initially off to isolate the high level on the fuse output lead, said second transistor is on, and said first transistor turns on in response to the high level of said first clock signal for pulling low the voltage at said other end of the fuse so as to hold said third transistor off, thus maintaining the fuse output lead at its high level and pulling the fuse output lead to a low level when the fuse is blown.

Claim 8

A redundancy scheme as set forth in claim 1 wherein the RAM includes row and column decoders for selecting a main row and column of memory cells, wherein the output data from each address buffer is coupled to said decoders for selecting a particular main row and column of memory cells, and further including decoder disabling circuitry receiving the control signal from said comparison means for causing the data output of each address buffer to assume a logic state selected to disable the decoders when said control signal is indicative of a match between incoming addresses and addresses stored in said address stores.

Claim 9

In a RAM having main columns of memory cells, a plurality of spare memory cells, a main decoder for accessing the main memory cells, and a spare decoder for accessing the spare memory cells, a redundancy scheme for replacing defective main cells with spare cells without disabling the main decoder, comprising: a memory array divided into first and second sectors, the first sector containing a portion of each main memory column and one or more spare columns, and the second sector containing the remaining portion of each main memory column and one or more spare columns; means for accessing the main memory columns and the spare memory columns such that, when a portion of an addressed main column in said first sector is defective and its remaining portion in said second sector is not defective, the non-defective portion of said addressed column is accessed and a spare replacement column in one of said sectors is accessed in place of the defective portion of the addressed column; and means for coupling the data associated with the accessed portion of the addressed column and the replacement spare column to a data output.

Claim 10

In a RAM having main columns of memory cells, a plurality of spare memory cells, a main decoder for accessing the main memory cells, and a spare decoder for accessing the spare memory cells, a redundancy scheme for replacing defective main cells with spare cells without disabling the main decoder, comprising: a memory array divided into first and second sectors, the first sector containing a portion of each main memory column and one or more spare columns, and the second sector containing the remaining portion of each main memory column and one or more spare columns; means for accessing the main memory columns and the spare memory columns such that, when a portion of an addressed main column in said first sector is defective and its remaining portion in said second sector is not defective, the non-defective portion of said addressed column is accessed and a spare replacement column in one of said sectors is accessed in place of the defective portion of the addressed column; and means for coupling the data associated with the accessed portion of the addressed column and the replacement spare column to a data output.

Claim 11

A redundancy scheme as set forth in claim 8 wherein said accessing means includes: a first main input/output buss for accessing the main memory column portions in the first memory sector; a first spare input/output buss for accessing the spare memory column in the first memory sector; a second main input/output buss for accessing the main memory column portions in the second memory sector; a second spare input/output buss for accessing the spare memory columns in the second memory sector; first logic-operated switch means for selectively coupling to the main input/output buss which accesses the non-defective portion of the addressed main column; second logic-operated switch means for selectively coupling to the spare input/output buss which accesses the replacement spare column; and means for coupling said first and second switch means to the data output so as to retrieve the data accessed by the I/O busses to which said first and second switch means are coupled.

Claim 12

In a RAM having a plurality of main rows and columns of memory cells, having a plurality of spare memory cells, and having a redundancy scheme for replacing defective main memory cells with spare memory cells, an address store for storing the address of a defective main cell, comprising: a fuse having one end thereof coupled to a positive voltage supply; a fuse-blowing transistor coupled to the other end of the fuse for carrying current so as to blow the fuse and thereby permanently store an indication that a memory address corresponds to the address of a defective main memory cell; fuse and fuse output leads for carrying logic data indicative of the state of the fuse; means for precharging the fuse and fuse output leads to high logic levels; a first transistor having its drain coupled to said other end of the fuse and adapted to receive at its gate a first clock signal selected to go from a low level to a high level; a second transistor having its drain coupled to the source of said first transistor and having a grounded source; a third transistor having its gate coupled to said other end of the fuse, having a source adapted to receive a second clock signal, and having a drain coupled to the gate of said second transistor; and means for selectively coupling said other end of the fuse to said fuse output lead and for simultaneously coupling the drain of said third transistor to said fuse output lead, said second clock signal being adapted to go to a low level from a high level a relatively short time after said first clock signal goes to a high level so that, when the fuse is blown, said third transistor is initially held off to isolate the high level on the fuse output lead, said second transistor is turned on, and said first transistor turns on in response to the high level of said first clock signal for pulling low the voltage at said other end of the fuse so as to hold said third transistor off, thus maintaining the fuse output lead at its high level and pulling the fuse output lead to a low level when the fuse is blown.

Claim 13

In a RAM having a plurality of main rows and columns of memory cells, having a plurality of spare memory cells, and having a redundancy scheme for replacing defective main memory cells with spare memory cells, an address store for storing the address of a defective main cell, comprising: a fuse having one end thereof coupled to a positive voltage supply; a fuse-blowing transistor coupled to the other end of the fuse for carrying current so as to blow the fuse and thereby permanently store an indication that a memory address corresponds to the address of a defective main memory cell; fuse and fuse output leads for carrying logic data indicative of the state of the fuse; means for precharging the fuse and fuse output leads to high logic levels; a first transistor having its drain coupled to said other end of the fuse and adapted to receive at its gate a first clock signal selected to go from a low level to a high level; a second transistor having its drain coupled to the source of said first transistor and having a grounded source; a third transistor having its gate coupled to said other end of the fuse, having a source adapted to receive a second clock signal, and having a drain coupled to the gate of said second transistor; and means for selectively coupling said other end of the fuse to said fuse output lead and for simultaneously coupling the drain of said third transistor to said fuse output lead, said second clock signal being adapted to go to a low level from a high level a relatively short time after said first clock signal goes to a high level so that, when the fuse is blown, said third transistor is initially held off to isolate the high level on the fuse output lead, said second transistor is turned on, and said first transistor turns on in response to the high level of said first clock signal for pulling low the voltage at said other end of the fuse so as to hold said third transistor off, thus maintaining the fuse output lead at its high level and pulling the fuse output lead to a low level when the fuse is blown.